Data Sheet
ADM1073
Rev. B | Page 3 of 24
GENERAL DESCRIPTION
(continued from Page 1)
Further control of the inrush current is provided by modulating
the width of the pulses, depending on the drain-source voltage
across the FET. This allows maximum charge transfer to the
load capacitance while maintaining the FET in its safe operating
area (SOA).
The default duty cycle of the pulse train is 6%, decreasing to
2.5% with maximum FET drain-source voltage, with a
maximum of seven successive autorestarts. After seven
successive autorestarts, the fault is latched and the part goes into
shutdown, with the result that the external FET is disabled until
the power is reset. The LATCHED
output signal indicates when
the seven retries are complete.
Further programmability is offered by allowing alteration of the
default 6% ratio. An extra resistor between the TIMER pin and
V
EE
allows the ratio of on-time to off-time to be decreased,
while a resistor between TIMER and V
IN
allows the ratio to be
increased.
The ADM1073 has separate UV and OV pins for undervoltage
and overvoltage detection. The FET is turned off, if a
nontransient voltage less than the undervoltage threshold
(typically 36 V) is detected on the UV pin, or if greater than
the overvoltage threshold (typically 80 V) is detected on the
OV pin. The operating voltage window of the ADM1073 is
programmable via resistor networks on the UV and OV pins.
The hysteresis levels on the undervoltage and overvoltage
detectors can also be altered (see the Undervoltage/Overvoltage
Detection section). The
SPLYGD
output signal indicates when
the backplane supply is within the externally programmable
operating voltage range.
Other functions include
"   PWRGD
output, which can be used to enable a power
module (the DRAIN pin is monitored to determine when
the load capacitance is fully charged)
"
SHDN
input to manually disable the GATE drive
"   RESTART
input to remotely initiate a 5 second shutdown
The ADM1073 is fabricated using BiCMOS technology for
minimal power consumption and is available in a 14-lead
TSSOP package.