參數(shù)資料
型號(hào)： ADM1073ARU-REEL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 15/24頁(yè)
文件大?。?/td> 370K
描述： IC CTRLR HOTSWAP -48V 14TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： -35 V ~ -80 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
配用： EVAL-ADM1073MEBZ-ND - BOARD EVALUATION FOR ADM1073
Data Sheet
ADM1073
 
Rev. B | Page 15 of 24
SENSE
The SENSE pin is used for sensing the voltage across an
external power sense resistor. This voltage is differentially
measured with respect to VEE, and used to control the GATE.
If SENSE is lower than 100 mV (after the soft start time), the
GATE pin is allowed to increase up to 12 V to provide
maximum FET enhancement. If the current increases such that
the SENSE pin tries to go above 100 mV, the GATE pin is
controlled in a feedback loop to ensure that the voltage across
the sense resistor is regulated at exactly 100 mV.
SENSE RESISTOR
The ADM1073s current limiting function can operate at
different current levels. The current limit is determined by
selection of the sense resistor, R
SENSE
. Table 4 shows how the
maximum allowable load current (I
LOAD(MAX)
) and the minimum
and maximum inrush currents (ILIMIT(MIN) and ILIMIT(MAX)) are
related to the value of RSENSE.
Table 4. Minumum and Maximum Inrush Current and Load
Current Levels for Different Values of R
SENSE
 
RSENSE (m&)
ILOAD(MAX) (A)   ILIMIT(MIN) (A) ILIMIT(MAX) (A)
5
17.20
19.40
20.60
10
8.60
9.70
10.30
15
5.73
6.47
6.87
18
4.78
5.39
5.72
22
3.91
4.41
4.68
33
2.61
2.94
3.12
47
1.83
2.06
2.19
51
1.69
1.90
2.02
68
1.26
1.43
1.51
75
1.15
1.29
1.37
90
0.96
1.08
1.14
 
SOFT START (SS PIN)
The SS pin is used to determine the inrush current profile.
A capacitor should be attached to this pin. Whenever the FET
is requested to turn on, the SS pin is held at ground until the
SENSE pin reaches a few mV. A current source is then turned
on, which linearly ramps the capacitor up to 2.5 V. The
reference voltage for the GATE linear control amplifier is
derived from the soft start voltage, such that the inrush linear
current limit is defined as
SENSE
START
SOFT
LIMIT
R
V
?/DIV>
=
20
/
_
 
Overdriving the SS Pin
The SS pin can be overdriven externally from 0.360 V to 1.95 V
to offset the current limit control loop threshold from 18 mV to
100 mV. This allows different current limits to be selected at
different points of operation without using multiple sense
resistors. The current limit voltage is clamped at 100 mV
maximum.
GATE
Analog output for driving the external FET gate. This pin is
switched to V
EE
 when the FET is off, is linearly controlled when
the FET is at the programmed inrush current limit, and is
switched to VIN when the FET is fully enhanced. The source
current capability is small to provide slow controlled turn-on,
and the sink current capability is large to provide fast turn-off.
V
IN
 
Positive supply pin. This current-driven supply is shunt-
regulated at 12.3 V internally, and should be connected to the
most positive input supply terminal (usually 48 V RTN or 0 V)
through a dropper resistor. The resistor should be chosen such
that it always supplies enough current to overcome the
maximum quiescent supply current of the chip. Default R
DROP
 =
30 k&.
V
EE
 
Negative supply input. This pin should be connected directly to
the most negative input supply terminal (48 V). This pin is
also used for differentially sensing across the external power
resistor, and should, therefore, be connected as close to the
sense resistor as possible. (See the Kelvin Sense Resistor
Connection section.)
TIMING CONTROLTIMER
The TIMER pin is an analog pin that determines the maximum
on-time when the FET is in linear current limit, and controls
the PWM duty cycle for pulsed load capacitor charging. A
capacitor should be attached to this pin. When the FET is in
current limit, a 19 礎(chǔ) current source charges the external
capacitor. If the FET is still in current limit when the TIMER
capacitor reaches 2.5 V, the GATE driver is turned off and a
1 礎(chǔ) discharge current sink is turned on. The GATE remains
low until the TIMER capacitor is reduced to 0.5 V. At this point,
the GATE pin is turned on again. If the FET goes back into
current limit, the TIMER recharging starts again.
The PWM duty cycle is set at 6% default level by the size of
these two current sources. Adding a resistor from TIMER to V
EE
 
decreases the duty cycle. Adding a resistor from TIMER to V
IN
 
increases the duty cycle.
In addition, a current proportional to the current into the
DRAIN pin is added to the charging current. The additional
current varies linearly with DRAIN voltage. This reduces the
maximum on-time and the percentage PWM duty cycle when
there is a large voltage across the FET.
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