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參數(shù)資料
| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統(tǒng)監(jiān)控/排序電路 |
| 文件頁數(shù)： | 29/45頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADM1060 |
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ADM1060 OUTPUTS
ADM1060
–
29
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
PR OGR A MMA BL E D R IVE R OUT PUT S
T he ADM1060 has 9 Programmable Driver Outputs
(PDO
’
s). T hese are the logic outputs of the device. Each
PDO is normally controlled by a PDB. T hus, the PDO
’
s
can be set up assert when the conditions on the PDB are
met (eg) the SFD
’
s are in tolerance, the levels on the GPI
are correct, the Watchdog timer has not timed out etc.
T he PDO
’
s can be used for a number of functions (eg)
provide a POWER_GOOD signal when all the SFD
’
s are
in tolerance, provide a reset generator output if one of the
SFD
’
s goes out of spec. (which can be used as a status
signal for a DSP or other microprocessor), provide enable
signals for LDO
’
s on the supplies that the ADM1060 is
supervising etc.
T here are a number of pull up options on the PDO
’
s to
enable the user to program the output level.
T he outputs can be programmed to be:-
Open Drain (allows the user to connect an external
pull- up resistor)
Open Drain with weak internal pull-up to V
DD
Open Drain with strong internal pull-up to V
DD
Open Drain with weak internal pull-up to VP_n
Open Drain with strong internal pull-up to VP_n
Internally charge-pumped high drive (+12V)
T he last option is only available on PDO1- 4. T his allows
the user to directly drive the gate of an N- Channel FET
in the path of a power supply. T he required pull- up is
selected by programming bits 0 to 3 in PnPDOCFG
appropriately (see table overleaf).
T he data driving each of the PDO
’
s can come from one of
3 inputs. T hese inputs are enabled by a bit each in the
PnPDOCFG registers. T he inputs are:-
T he (delayed) output from the associated PLB (enabled
by setting bit CFG4 to 1)
Data which is driven directly over the SMBus interface
(enabled by setting bit CFG5 to1). When set in this
mode, the data from the PDB is disabled and the data on
the PDO is the data on CFG4. T hus the PDO can be
software controlled (eg) to initiate a software power up/
powerdown.
An On- Chip Clock (enabled by setting bit CFG6 to1).
A 100K Hz clock is available to clock an external device
(eg) a LED.
More detail of these data modes is given in the register
map overleaf.
T he default setup of each of the PDO
’
s is to be pulled low
by a weak (20k ) pulldown resistor. T his is also the setup
of the PDO
’
s on power- up until the registers are loaded
and the programmed conditions are latched. T he outputs
are actively pulled low once 1V or greater is seen at any of
VPn or VH. Until there is a 1V supply on the chip the
outputs are high impedance. T his provides a known
condition for the PDO
’
s during power- up. T he pulldown
can be overdriven if required (eg) tie an external pull- up
resistor to the PDO to ensure that the gate of a PMOS
device was not turned on.
T he register list and the bit map for the PDO
’
s is shown
below.
Figure 7. Programmable Driver Output
SEL
VP1
VP4
VDD
M_CLK
PDO
PDB_OUT
C
C
C
2
V
2
V
2
V
CFG4
VFET (PDO1-4 ONLY)
2
V
1
V
1
V
1
V
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