參數(shù)資料
型號(hào): ADM1060
廠(chǎng)商: Analog Devices, Inc.
英文描述: DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes
中文描述: 通信系統(tǒng)監(jiān)控/排序電路
文件頁(yè)數(shù): 24/45頁(yè)
文件大?。?/td> 303K
代理商: ADM1060
ADM1060
ADM1060 LOGIC
24
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
PLBA REGISTER BITMAPS
T ABL E 28. BIT MAP F OR PnPL BPOL A/PnPL BPOL B RE GIST E RS (POWE R- ON D E F AUL T 00H)
Bit
Name
R/W
Description
7-0
POL 9-POL 1
R /W
If high,
invert
the
PLBn
input before it is used in function A or B
PLB1
PLB2
PLB3
PLB4
PLB5
PLB6
PLB7
PLB8
PLB9
Function A
00H
10H
20H
30H
40H
50H
60H
70H
80H
Function B
08H
18H
28H
38H
48H
58H
68H
78H
88H
7
PL B9
PL B9
PL B9
PL B9
PL B9
PL B9
PL B9
PL B9
PL B8
6
PL B8
PL B8
PL B8
PL B8
PL B8
PL B8
PL B8
PL B7
PL B7
5
PL B7
PL B7
PL B7
PL B7
PL B7
PL B7
PL B6
PL B6
PL B6
4
PL B6
PL B6
PL B6
PL B6
PL B6
PL B5
PL B5
PL B5
PL B5
3
PL B5
PL B5
PL B5
PL B5
PL B4
PL B4
PL B4
PL B4
PL B4
2
PL B4
PL B4
PL B4
PL B3
PL B3
PL B3
PL B3
PL B3
PL B3
1
PL B3
PL B3
PL B2
PL B2
PL B2
PL B2
PL B2
PL B2
PL B2
0
PL B2
PL B1
PL B1
PL B1
PL B1
PL B1
PL B1
PL B1
PL B1
T ABL E 29. BIT MAP F OR PnPL BIMK A/PnPL BIMK B RE GIST E RS (POWE R- ON DE F AUL T 00H)
Bit
Name
R/W
Description
7-0
IG N9-IG N1
R /W
If high,
mask
the
PLBn
input before it is used in function A or B
PLB1
PLB2
PLB3
PLB4
PLB5
PLB6
PLB7
PLB8
PLB9
Function A
01H
11H
21H
31H
41H
51H
61H
71H
81H
Function B
09H
19H
29H
39H
49H
59H
69H
79H
89H
7
PL B9
PL B9
PL B9
PL B9
PL B9
PL B9
PL B9
PL B9
PL B8
6
PL B8
PL B8
PL B8
PL B8
PL B8
PL B8
PL B8
PL B7
PL B7
5
PL B7
PL B7
PL B7
PL B7
PL B7
PL B7
PL B6
PL B6
PL B6
4
PL B6
PL B6
PL B6
PL B6
PL B6
PL B5
PL B5
PL B5
PL B5
3
PL B5
PL B5
PL B5
PL B5
PL B4
PL B4
PL B4
PL B4
PL B4
2
PL B4
PL B4
PL B4
PL B3
PL B3
PL B3
PL B3
PL B3
PL B3
1
PL B3
PL B3
PL B2
PL B2
PL B2
PL B2
PL B2
PL B2
PL B2
0
PL B2
PL B1
PL B1
PL B1
PL B1
PL B1
PL B1
PL B1
PL B1
T ABL E 30. BIT MAP F OR PnSF D POL A/PnSF D POL B RE GIST E RS (POWE R- ON D E F AUL T 00H)
Bit
Name
R/W
Description
7
Reserved N/A
Cannot be used
6-0
POL 7-POL 1
R /W
If high,
invert
the
SFDn
input before it is used in function A or B
PLB1
PLB2
PLB3
PLB4
PLB5
PLB6
PLB7
PLB8
PLB9
Function A
02H
12H
22H
32H
42H
52H
62H
72H
82H
Function B
0AH
1AH
2AH
3AH
4AH
5AH
6AH
7AH
8AH
6
V P4
V P4
V P4
V P4
V P4
V P4
V P4
V P4
V P4
5
V P3
V P3
V P3
V P3
V P3
V P3
V P3
V P3
V P3
4
V P2
V P2
V P2
V P2
V P2
V P2
V P2
V P2
V P2
3
V P1
V P1
V P1
V P1
V P1
V P1
V P1
V P1
V P1
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