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參數(shù)資料
| 型號： | ADM1031ARQZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | LEAD FREE, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 596K |
| 代理商： | ADM1031ARQZ |
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ADM1031
Rev. B | Page 19 of 36
FILTERED CONTROL MODE
The automatic fan speed control loop reacts instantaneously to
changes in temperature, that is, the PWM duty cycle responds
immediately to temperature change. In certain circumstances,
we do not want the PWM output to react instantaneously to
temperature changes. If significant variations in temperature are
found in a system, the fan speed changes, which could be
obvious to someone in close proximity. One way to improve the
system’s acoustics would be to slow down the loop so that the
fan ramps slowly to its newly calculated fan speed. This also
ensures that temperature transients are effectively ignored, and
the fan’s operation is smooth.
There are two means by which to apply filtering to the
automatic fan speed control loop. The first method is to ramp
the fan speed at a predetermined rate, to its newly calculated
value instead of jumping directly to the new fan speed. The
second approach involves changing the on-chip ADC sample
rate, to change the number of temperature readings taken per
second.
The filtered mode on the ADM1031 is invoked by setting Bit 0
of the fan filter register (Register 0×23) for Fan 1 and Bit 1 for
Fan 2. Once the fan filter register has been written to, and all
other control loop parameters (such as TMIN, TRANGE) have been
programmed, the device can be placed into automatic fan speed
control mode by setting Bit 7 of Configuration Register 1
(Register 0×00) to 1.
Effect of Ramp Rate on Filtered Mode
Bits <6:5> of the fan filter register determine the ramp rate in
filtered mode. The PWM_OUT signal driving the fan has a
period, T, given by the PWM_OUT drive frequency, f, since T =
1/f. For a given PWM period, T, the PWM period is subdivided
in to 240 equal time slots. One time slot corresponds to the
smallest possible increment in PWM duty cycle. A PWM signal
of 33% duty cycle is thus high for 1/3 × 240 time slots and low
for 2/3 × 240 time slots. Therefore, 33% PWM duty cycle
corresponds to a signal that is high for 80 time slots and low for
160 time slots.
PWM_OUT
33% DUTY
CYCLE
80 TIME
SLOTS
160 TIME
SLOTS
PWM OUTPUT
(ONE PERIOD =
240 TIME SLOTS
02402-028
Figure 28. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in filtered mode are selectable between 1, 2, 4,
and 8. The ramp rates are actually discrete time slots. For
example, if the ramp rate = 8, then eight time slots are added to
the PWM_OUT high duty cycle each time the PWM_OUT
duty cycle needs to be increased. Figure 29 shows how the
filtered mode algorithm operates.
READ
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
INCREMENT
PREVIOUS PWM
VALUE BY RAMP
RATE
DECREMENT
PREVIOUS
PWM VALUE
BY RAMP
RATE
IS NEW
PWM VALUE >
PREVIOUS
VALUE?
YES
NO
02402-029
Figure 29. Filtered Mode Algorithm
The filtered mode algorithm calculates a new PWM duty cycle
based on the temperature measured. If the new PWM duty
cycle value is greater than the previous PWM value, the
previous PWM duty cycle value is incremented by either 1, 2, 4,
or 8 time slots (depending on the setting of bits <6:5> of the fan
filter register). If the new PWM duty cycle value is less than the
previous PWM value, the previous PWM duty cycle is
decremented by 1, 2, 4, or 8 time slots. Each time the PWM
duty cycle is incremented or decremented, it is stored as the
previous PWM duty cycle for the next comparison.
What does an increase of 1, 2, 4, or 8 time slots actually
mean in terms of PWM duty cycle?
A ramp rate of 1 corresponds to one time slot, which is 1/240
of the PWM period. In filtered auto fan speed control mode,
incrementing or decrementing by 1 changes the PWM output
duty cycle by 0.416%.
Table 12. Effect of Ramp Rates on PWM_OUT
Ramp Rate
PWM Duty Cycle Change
1
0.416%
2
0.833%
4
1.66%
8
3.33%
So programming a ramp rate of 1, 2, 4, or 8 simply increases
or decreases the PWM duty cycle by the amounts shown in
Table 12, depending on whether the temperature is increasing
or decreasing.
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