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參數(shù)資料
| 型號： | ADF4360-8BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24-LFCSP |
| 標準包裝： | 1 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 其它名稱： | ADF4360-8BCPZRL7DKR |
ADF4360-8
Rev. A | Page 10 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
04763-016
BUFFER
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
Figure 16. Reference Input Stage
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is re-
ferred to as the B counter. It makes it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The VCO frequency equation is
R
f
B
f
REFIN
VCO
/
×
=
where:
fVCO
is the output frequency of the VCO.
B
is the preset divide ratio of the binary 13-bit counter (3 to 8191).
fREFIN
is the external reference frequency oscillator.
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 17 is a simpli-
fied schematic. The PFD includes a programmable delay ele-
ment that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function, and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width of
the pulse (see Table 9).
04763-
017
PROGRAMMABLE
DELAY
U3
CLR2
Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HI
U1
ABP1
ABP2
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
VP
Figure 17. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 18 shows
the MUXOUT section in block diagram form.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DVDD
04763-018
Figure 18. MUXOUT Circuit
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| ADF4360-9BCPZ | 功能描述:IC SYNTHESIZER W/ADJ VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-9BCPZRL | 功能描述:IC SYNTHESIZER W/ADJ VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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