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參數(shù)資料
| 型號： | ADF4218LBRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.6 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. C
ADF4217L/ADF4218L/ADF4219L
–6–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
VDD1Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same
potential as VDD2.
VP1Power Supply for the RF Charge Pump. This should be greater than or equal to VDD.
CPRF
Output from the RF Charge Pump. When enabled, this provides
±I
CP to the external loop filter, which in turn
drives the external VCO.
DGNDRF
Ground Pin for the RF Digital Circuitry
RFINA
Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
RFINBComplementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
AGNDRF
Ground Pin for the RF Analog Circuitry
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 k
. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.
DGNDIF
Ground Pin for the IF Digital, Interface, and Control Circuitry
MUXOUT
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally (Table V).
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches; the latch is selected using the control bits.
AGNDIF
Ground Pin for the IF Analog Circuitry
NC
This pin is not connected internally (ADF4219L only).
IFINBComplementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF (ADF4217L/ADF4218L only).
IFINA
Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
DGNDIF
Ground Pin for the IF Digital, Interface, and Control Circuitry
CPIF
Output from the IF Charge Pump. When enabled, this provides
±I
CP to the external loop filter, which in turn drives
the external VCO.
VP2Power Supply for the IF Charge Pump. This should be greater than or equal to VDD.
VDD2Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V.
VDD2 must have the same potential as VDD1.
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