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參數(shù)資料
| 型號(hào)： | ADF4218LBRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.6 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. C
ADF4217L/ADF4218L/ADF4219L
–10–
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fP
B
A
f
R
VCO
REF
IN
=×
()+
[]×
/
fVCO = Output frequency of external voltage controlled oscillator
(VCO).
P
= Preset modulus of dual modulus prescaler (8/9, 16/17, and
so on).
B
= Preset divide ratio of binary 11-bit counter (ADF4217L/
ADF4218L), binary 13-bit counter (ADF4219L).
A
= Preset divide ratio of binary 6-bit A counter (ADF4217L/
ADF4218L), binary 5-bit counter (ADF4219L).
fREF
IN =Output frequency of the external reference frequency
oscillator.
R
= Preset divide ratio of binary 14-bit programmable reference
counter (1 to 16383). The ADF4219L has an R divide
of 15 bits.
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed. The
extra R15 bit on the ADF4219L allows ratios from 1 to 32767.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplied schematic.
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
D1
Q1
CLR1
U1
U3
DELAY
ELEMENT
HI
UP
D2
Q2
CLR2
U2
HI
DOWN
VP
CHARGE
PUMP
CP
CPGND
Figure 5. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4217L family allows the user
to access various internal points on the chip. The state of MUXOUT
is controlled by P3, P4, P11, and P12. See Tables IV and VII.
Figure 6 shows the MUXOUT section in block diagram form.
IF ANALOG LOCK DETECT
IF R COUNTER OUTPUT
IF N COUNTER OUTPUT
IF/RF ANALOG LOCK DETECT
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
RF ANALOG LOCK DETECT
MUX
CONTROL
MUXOUT
DVDD
DGND
Figure 6. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 k
nominal. When lock
has been detected, it is high with narrow low going pulses.
INPUT SHIFT REGISTER
The functional block diagram for the ADF4217L family is shown
on page 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and an N counter. The N counter is comprised
of a 6-bit A counter and an 11-bit B counter for the ADF4217L
and the ADF4218L. The 18-bit N counter on the ADF4219L
is comprised of a 13-bit B counter and a 5-bit A counter. Data
is clocked into the 22-bit shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the shift register to one of four latches on the rising edge of LE.
The destination latch is determined by the state of the two con-
trol bits (C2, C1) in the shift register. These are the two LSBs,
DB1 and DB0, as shown in the timing diagram of Figure 1. The
truth table for these bits is shown in Table I.
Table I. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
00
IF R Counter
01
IF AB Counter (and Prescaler Select)
10
RF R Counter
11
RF AB Counter (and Prescaler Select)
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