t3 t1
參數(shù)資料
型號： ADF4218LBRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 18/24頁
文件大?。?/td> 0K
描述： IC PLL FREQ SYNTHESIZER 20TSSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時鐘/頻率合成器（RF/IF）
PLL： 是
輸入： CMOS，TTL
輸出： 時鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:1
差分 - 輸入:輸出： 是/無
頻率 - 最大： 3GHz
除法器/乘法器： 是/無
電源電壓： 2.6 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
REV. C
–3–
ADF4217L/ADF4218L/ADF4219L
CLOCK
DATA
LE
t3
t1
t2
t4
t5
t6
DB21 (MSB)
DB20
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
Figure 1. Timing Diagram
BChips
2
Parameter
B Version
1
(Typical)
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
6
RF Phase Noise Floor
7
–171
dBc/Hz typ
@ 30 kHz PFD Frequency
–163
dBc/Hz typ
@ 200 kHz PFD Frequency
IF Phase Noise Floor
7
–167
dBc/Hz typ
@ 30 kHz PFD Frequency
–159
dBc/Hz typ
@ 200 kHz PFD Frequency
Phase Noise Performance
8
@ VCO Output
RF
9
–75
dBc/Hz typ
1.95 GHz Output; 30 kHz PFD
RF
10
–90
dBc/Hz typ
900 MHz Output; 200 kHz PFD
IF
11
–77
dBc/Hz typ
900 MHz Output; 30 kHz PFD
IF
12
–86
dBc/Hz typ
900 MHz Output; 200 kHz PFD
Spurious Signals
Measured at Offset of fPFD/2fPFD
RF
9
–78/–85
dBc typ
RF
10
–80/–84
dBc typ
IF
11
–79/–86
dBc typ
IF
12
–80/–84
dBc typ
NOTES
1Operating temperature range is as follows: B Version: –40
°C to +85°C.
2The BChip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
4Guaranteed by design. Sample tested to ensure compliance.
5This includes relevant I
P.
6V
DD = 3 V; P = 16/32; IFIN /RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
8The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN
for the synthesizer. (fREFOUT = 10 MHz @ 0 dBm.)
9f
REFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fRF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz
10f
REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz
11f
REFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 30000; Loop B/W = 3 kHz
12f
REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f IF = 900 MHz; N = 4500; Loop B/W = 20 kHz
Specifications subject to change without notice.
Limit at
TMIN to TMAX
Parameter
(B Version)
Unit
Test Conditions/Comments
t1
10
ns min
DATA to CLOCK Setup Time
t2
10
ns min
DATA to CLOCK Hold Time
t3
25
ns min
CLOCK High Duration
t4
25
ns min
CLOCK Low Duration
t5
10
ns min
CLOCK to LE Setup Time
t6
50
ns min
LE Pulsewidth
Guaranteed by design but not production tested.
TIMING CHARACTERISTICS (V
DD1 = VDD2 = 3 V
10%, 5 V
10%; VDD1, VDD2
≤ VP1,
VP2
≤ 6.0 V ; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
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