Typical (typ) values are given for V" />
參數(shù)資料
型號(hào): ADCLK946/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL CLK BUFF ADCLK946
設(shè)計(jì)資源: ADCLK946 Schematic
ADCLK946 Gerber File
ADCLK946 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘緩沖器 / 驅(qū)動(dòng)器 / 接收器 / 變換器
嵌入式:
已用 IC / 零件: ADCLK946
主要屬性: 1 輸入,6 輸出
次要屬性: LVPECL 輸出邏輯
已供物品:
ADCLK946
Rev. A | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (typ) values are given for VCC VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values
are given over the full VCC VEE = 3.3 V ± 10% and TA = 40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Voltage High Level
VIH
VEE + 1.6
VCC
V
Input Voltage Low Level
VIL
VEE
VCC 0.2
V
Input Differential Range
VID
0.4
3.4
V p-p
±1.7 V between input pins
Input Capacitance
CIN
0.4
pF
Input Resistance
Single-Ended Mode
50
Differential Mode
100
Common Mode
50
k
Open VT
Input Bias Current
20
A
Hysteresis
10
mV
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
VOH
VCC 1.26
VCC 0.76
V
50 to (VCC 2.0 V)
Output Voltage Low Level
VOL
VCC 1.99
VCC 1.54
V
50 to (VCC 2.0 V)
Output Voltage, Single-Ended
VO
610
960
mV
VOH VOL, output static
Reference Voltage
VREF
Output Voltage
(VCC + 1)/2
V
500 A to +500 A
Output Resistance
235
Table 2. Timing Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency
4.5
4.8
GHz
See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
Output Rise/Fall Time
tR, tF
40
75
90
ps
20% to 80% measured differentially
Propagation Delay
tPD
150
185
220
ps
VICM = 2 V, VID = 1.6 V p-p
Temperature Coefficient
50
fs/°C
Output-to-Output Skew
9
28
ps
Part-to-Part Skew1
45
ps
VID = 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter
28
fs rms
BW = 12 kHz 20 MHz, CLK = 1 GHz
Broadband Random Jitter2
75
fs rms
VID = 1.6 V p-p, 8 V/ns, VICM = 2 V
Crosstalk-Induced Jitter3
90
fs rms
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
Input slew rate > 1 V/ns (see Figure 11 for more details)
fIN = 1 GHz
119
dBc/Hz
@ 100 Hz offset
134
dBc/Hz
@ 1 kHz offset
145
dBc/Hz
@ 10 kHz offset
150
dBc/Hz
@ 100 kHz offset
150
dBc/Hz
>1 MHz offset
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3
The amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
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