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參數(shù)資料
| 型號(hào)： | ADCLK946/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL CLK BUFF ADCLK946 |
| 設(shè)計(jì)資源： | ADCLK946 Schematic ADCLK946 Gerber File ADCLK946 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘緩沖器 / 驅(qū)動(dòng)器 / 接收器 / 變換器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCLK946 |
| 主要屬性： | 1 輸入，6 輸出 |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
ADCLK946
Rev. A | Page 10 of 12
PCB LAYOUT CONSIDERATIONS
The ADCLK946 buffer is designed for very high speed
applications. Consequently, high speed design techniques must
be used to achieve the specified performance. It is critically
important to use low impedance supply planes for both the
negative supply (VEE) and the positive supply (VCC) planes as
part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
The following references to the ground plane assume that
the VEE power plane is grounded for LVPECL operation.
Note that, for ECL operation, the VCC power plane becomes
the ground plane.
It is also important to adequately bypass the input and output
supplies. Place a 1 F electrolytic bypass capacitor within several
inches of each VCC power supply pin to the ground plane. In
addition, place multiple high quality 0.001 F bypass capacitors
as close as possible to each of the VCC supply pins, and connect
the capacitors to the ground plane with redundant vias.
Carefully select high frequency bypass capacitors for minimum
inductance and ESR. To improve the effectiveness of the bypass
at high frequencies, minimize parasitic layout inductance. Also,
avoid discontinuities along input and output transmission lines
that can affect jitter performance.
In a 50 environment, input and output matching have a
significant impact on performance. The buffer provides internal
50 termination resistors for both CLK and CLK inputs.
Normally, the return side is connected to the reference pin that is
provided. Carefully bypass the termination potential using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If the inputs are dc-coupled to a source, take care to
ensure that the pins are within the rated input differential and
common-mode ranges.
If the return is floated, the device exhibits a 100 Ω cross-
termination, but the source must then control the common-
mode voltage and supply the input bias currents.
There are ESD/clamp diodes between the input pins to prevent
the application from developing excessive offsets to the input
transistors. ESD diodes are not optimized for best ac perfor-
mance. When a clamp is required, it is recommended that
appropriate external diodes be used.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK946 package is both
an electrical connection and a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to the VEE pin.
When properly mounted, the ADCLK946 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK946. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
The ADCLK946 evaluation board (ADCLK946/PCBZ)
provides an example of how to attach the part to the PCB.
VIAS TO VEE POWER
PLANE
08053-
018
Figure 18. PCB Land for Attaching Exposed Paddle
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCLK948 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer |
| ADCLK948/PCBZ | 功能描述:BOARD EVALUATION FOR ADCLK948 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SIGe 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| ADCLK948BCPZ | 功能描述:IC CLOCK BUFFER MUX 2:8 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| ADCLK948BCPZ | 制造商:Analog Devices 功能描述:CLOCK FANOUT BUFFER, 4.8GHZ, LFCSP-32 |
| ADCLK948BCPZ-REEL7 | 功能描述:IC CLOCK BUFFER MUX 2:8 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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