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參數(shù)資料
| 型號： | ADC16061 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter(16位2.5 MSPS,390 mW可自行校對的A/D轉(zhuǎn)換器) |
| 中文描述： | 自校準(zhǔn)16位，250 MSPS的，390毫瓦的A / D轉(zhuǎn)換器（16位250 MSPS的，390毫瓦可自行校對的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 476K |
| 代理商： | ADC16061 |
Pin Descriptions and Equivalent Circuits
(Continued)
Digital I/O
10
CLOCK
Digital clock input. The input voltage is captured t
AD
after the fall of
the clock signal. The range of frequencies for this input is 300 kHz
to 2.5 MHz. The clock frequency should not be changed or
interrupted during conversion or while reading data output.
11
CAL
CAL is a level-sensitive digital input that, when pulsed high for at
least two clock cycles, puts the ADC into the CALIBRATE mode.
Calibration should be performed upon ADC power-up (after
asserting a reset) and each time the temperature changes by more
than 50C since the ADC16061 was last calibrated. See Section
2.3 for more information.
RESET is a level-sensitive digital input that, when pulsed high for
at least 2 CLOCK cycles, results in the resetting of the ADC. This
reset pulse must be applied after ADC power-up, before
calibration.
RD is the (READ) digital input that, when low, enables the output
data buffers. When this input pin is high, the output data bus is in
a high impedance state.
PD is the Power Down input that, when low, puts the converter
into the power down mode. When this pin is high, the converter is
in the active mode.
40
RESET
18
RD
44
PD
17
EOC
EOC is a digital output that, when low, indicates the availability of
new conversion results at the data output pins.
21-32
35-38
D00-15
Digital data outputs that make up the 16-bit TRI-STATE conversion
results. D00 is the LSB, while D15 is the MSB (SIGN bit) of the
two’s complement output word.
Analog Power
6, 7,
45
V
A
Positive analog supply pins. These pins should be connected to a
clean, quiet +5V source and bypassed to AGND with 0.1 μF
monolithic capacitors in parallel with 10 μF capacitors, both located
within 1 cm of these power pins.
The ground return for the analog supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and grounding) for more details).
5, 8,
46
AGND
A
www.national.com
4
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