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參數(shù)資料
| 型號： | ADC16061 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter(16位2.5 MSPS,390 mW可自行校對的A/D轉(zhuǎn)換器) |
| 中文描述： | 自校準16位，250 MSPS的，390毫瓦的A / D轉(zhuǎn)換器（16位250 MSPS的，390毫瓦可自行校對的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 476K |
| 代理商： | ADC16061 |
Applications Information
(Continued)
V
REF
OUT
= V
CM
1
2
V
REF
where V
REF
= (V
REF
+
IN
) (V
REF
+ IN)
V
REF (MID)
= (V
REF
+
OUT
+ V
REF
OUT
) / 2.
To avoid signal clipping and distortion, V
+
should not
exceed 3.3V, V
should not be below 750 mV and
V
CM
should be held in the range of 1.8V to 2.2V.
3.2 The EOC output
goes low to indicate the presence of
valid data at the output data lines. Valid data is present the
entire time that this signal is low, except during reset. Corrupt
or irrelevant data may appear at the data outputs when the
RESET pin or the CAL pin is high.
3.3 The Data Outputs
are TTL/CMOS compatible. The out-
put data format is two’s complement. Valid data is present at
these outputs while the EOC pin is low. While the t
time
and the t
time provide information about output
timing, a simple way to capture a valid output is to latch the
data on the rising edge of the CLOCK (pin 10).
Also helpful in minimizing noise due to output switching is to
minimize the load currents at the digital outputs. This can be
done by connecting buffers between the ADC outputs and
any other circuitry. Only one input should be connected to
each output pin. Additionally, inserting series resistors of 47
or 56 Ohms at the digital outputs, close to the ADC pins, will
isolate the outputs from other circuitry and limit output cur-
rents. (See Figure 6).
4.0 POWER SUPPLY CONSIDERATIONS
Each power supply pin should be bypassed with a parallel
combination of a 10 μF capacitor and a 0.1 μF ceramic chip
capacitor. The chip capacitors should be within
1
2
centimeter
of the power pins. Leadless chip capacitors are preferred
because they provide low lead inductance.
While a single 5V source is used for the analog and digital
supplies of the ADC16061, these supply pins should be well
isolated from each other to prevent any digital noise from
being coupled to the analog power pins. Supply isolation
with ferrite beads is shown in Figure 6 and Figure 8
As is the case with all high-speed converters, the ADC16061
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 15 mV
P-P
.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even during power up or power
down.
The V
I/O provides power for the output drivers and may be
operated from a supply in the range of 2.7V to the V
supply
(nominal 5V). This can simplify interfacing to 3.0 Volt devices
and systems. Powering V
I/O from 3 Volts will also reduce
power consumption and noise generation due to output
switching.
DO NOT operate the V
D
I/O at a voltage higher
than V
D
or V
A
.
DS100889-19
FIGURE 6. Simple application circuit with single-ended to differential buffer.
A
www.national.com
15
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