I2C Read and Write Operations Figure 51 shows th" />
參數(shù)資料
型號(hào)： ADAU1761BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/92頁(yè)
文件大小： 0K
描述： IC SIGMADSP CODEC PLL 32LFCSP
設(shè)計(jì)資源： Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078)
標(biāo)準(zhǔn)包裝： 5,000
系列： SigmaDSP®
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63V ~ 3.65V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
配用： EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761
ADAU1761
Rev. C | Page 40 of 92
I2C Read and Write Operations
Figure 51 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1761 issues an acknowledge
by pulling SDA low.
Figure 52 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1761 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length.
Figure 53 shows the format of a single-word read operation. Note
that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1761 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W bit set to 1 (read).
This causes the ADAU1761 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1761.
Figure 54 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1761 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length. The
ADAU1761 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 51 to Figure 54 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
Chip address,
R/W = 0
AS
Subaddress high byte
AS
Subaddress low byte
AS
Data Byte 1
P
Figure 51. Single-Word I2C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high byte
AS
Subaddress
low byte
AS
Data
Byte 1
AS
Data
Byte 2
AS
Data
Byte 3
AS
Data
Byte 4
AS
…
P
Figure 52. Burst Mode I2C Write Format
S
Chip address,
R/W = 0
AS
Subaddress high
byte
AS
Subaddress low
byte
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
P
Figure 53. Single-Word I2C Read Format
S
Chip address,
R/W = 0
AS
Subaddress
high byte
AS
Subaddress
low byte
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
AM
Data
Byte 2
AM
…
P
Figure 54. Burst Mode I2C Read Format
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