參數(shù)資料
型號: ADATE207BBPZ
廠商: Analog Devices Inc
文件頁數(shù): 20/36頁
文件大小: 0K
描述: IC TIMING FORMATTER QUAD 256BGA
標(biāo)準(zhǔn)包裝: 1
類型: 四針定時格式器
PLL:
主要目的: 自動測試設(shè)備
電路數(shù): 4
頻率 - 最大: 100MHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 256-BGA(27x27)
包裝: 托盤
ADATE207
Rev. 0 | Page 27 of 36
Name:
Waveform D2 Vernier Delay and Action
Address:
0x0A
Type:
Read/Write
Table 24. Waveform D2 Vernier Delay and Action
Position
Description
Reset State
Bits[15:10]
D2 Vernier Delay: The vernier delay is represented in binary by the equation,
vvvvvv × (2.5 ns/64)
Undefined
Bits[09:04]
Not Used.
0x00
Bits[03:00]
D2 Action. A binary encoded data field.
Undefined
0x0 = no action.
0x1 = drive low.
0x2 = drive high.
0x3 = force off.
0x4 = force on.
0x5 = force down.
0x6 = force up.
0x7 = edge compare low.
0x8 = edge compare high.
0x9 = edge compare off.
0xA = edge compare valid.
0xB = open window low.
0xC = open window high.
0xD = open window high-Z.
0xE = open window valid.
0xF = compare unknown.
Name:
Waveform D2 Course Delay
Address:
0x0B
Type:
Read/Write
Table 25. Waveform D2 Course Delay
Position
Description
Reset State
Bits[15:00]
D2 Course Delay. Number of 2.5 ns clock periods to count.
Undefined
When this count is completed, the vernier delay (defined by the D2 vernier value programmed
into the waveform D2 vernier delay and action register) is added to the D2 course delay to
place an edge in time
Waveform D2 vernier delay and action must be written immediately before this register for the
waveform memory to be correctly written.
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