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參數(shù)資料
| 型號： | ADF4002BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 16-TSSOP |
| 設計資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器（RF），相位檢測器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
Phase Detector/Frequency Synthesizer
Data Sheet
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2006–2012 Analog Devices, Inc. All rights reserved.
FEATURES
400 MHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase detector
APPLICATIONS
Clock conditioning
Clock generation
IF LO generation
GENERAL DESCRIPTION
The ADF4002 frequency synthesizer is used to implement local
oscillators in the upconversion and downconversion sections of
wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge
pump, a programmable reference divider, and programmable
N divider. The 14-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled
oscillator (VCO). In addition, by programming R and N to 1,
the part can be used as a standalone PFD and charge pump.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
REFIN
RFINA
RFINB
24-BIT INPUT
REGISTER
SDOUT
AVDD
DVDD
CE
AGND
DGND
14-BIT
R COUNTER
LATCH
22
14
FUNCTION
LATCH
N COUNTER
LATCH
13-BIT
N COUNTER
M3 M2 M1
MUX
SDOUT
AVDD
HIGH Z
MUXOUT
CPGND
RSET
VP
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4002
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
CURRENT
SETTING 2
06052-
001
Figure 1.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4002SRU-EP | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Rail/Tube 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRU-EP-RL7 | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Tape and Reel 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRUZ-EP | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:96 |
| ADF4002SRUZ-EP-RL7 | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:1,000 |
| ADF4007 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Frequency Divider/PLL Synthesizer |
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