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參數(shù)資料
| 型號： | ADF4002BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 16-TSSOP |
| 設(shè)計(jì)資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率合成器（RF），相位檢測器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
Data Sheet
ADF4002
Rev. C | Page 3 of 20
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 ,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
See Figure 11 for input circuit
RF Input Sensitivity
10
0
dBm
RF Input Frequency (RFIN)
5
400
MHz
For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/s
REFIN CHARACTERISTICS
REFIN Input Frequency
20
300
MHz
For REFIN < 20 MHz, ensure SR > 50 V/s
REFIN Input Sensitivity2
0.8
VDD
V p-p
Biased at AVDD/23
REFIN Input Capacitance
10
pF
REFIN Input Current
±100
A
PHASE DETECTOR
Phase Detector Frequency4
104
MHz
ABP = 0, 0 (2.9 ns antibacklash pulse width)
CHARGE PUMP
Programmable, see Figure 18
ICP Sink/Source
High Value
5
mA
With RSET = 5.1 k
Low Value
625
A
Absolute Accuracy
2.5
%
With RSET = 5.1 k
RSET Range
3.0
11
k
ICP Three-State Leakage
1
nA
TA = 25°C
ICP vs. VCP
1.5
%
0.5 V ≤ VCP ≤ VP 0.5 V
Sink and Source Current Matching
2
%
0.5 V ≤ VCP ≤ VP 0.5 V
ICP vs. Temperature
2
%
VCP = VP/2
LOGIC INPUTS
VIH, Input High Voltage
1.4
V
VIL, Input Low Voltage
0.6
V
IINH, IINL, Input Current
±1
A
CIN, Input Capacitance
10
pF
LOGIC OUTPUTS
VOH, Output High Voltage
1.4
V
Open-drain output chosen, 1 k pull-up resistor to 1.8 V
VOH, Output High Voltage
VDD 0.4
V
CMOS output chosen
IOH
100
A
VOL, Output Low Voltage
0.4
V
IOL = 500 A
POWER SUPPLIES
AVDD
2.7
3.3
V
DVDD
AVDD
VP
AVDD
5.5
V
AVDD ≤ VP ≤ 5.5 V
5.0
6.0
mA
IP
0.4
mA
TA = 25°C
Power-Down Mode
1
A
AIDD + DIDD
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