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參數(shù)資料
| 型號： | ADADC80-Z-12 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT INTEGRATED 32-CDIP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-CDIP（0.910"，23.12mm） |
| 供應(yīng)商設(shè)備封裝： | 32-CDIP 側(cè)面銅焊 |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極 |
ADADC80
Rev. E | Page 9 of 16
DIGITAL OUTPUT DATA
Parallel data from TTL storage registers is in negative true form.
Parallel data output coding is complementary binary for
unipolar ranges and either complementary offset binary or
complementary twos complement binary for bipolar ranges,
depending on whether BIT 1 (Pin 6) or its logical inverse
BIT 1 (MSB) (Pin 8) is used as the MSB. Parallel data becomes
valid approximately 40 ns before the STATUS flag returns to
Logic 0, permitting parallel data transfer to be clocked on the
1 to 0 transition of the STATUS flag.
Parallel data outputs change state on positive-going clock edges.
There are 13 negative-going clock edges in the complete 12-bit
conversion cycle, as shown in Figure 7. The first edge shifts an
invalid bit into the register, which is shifted out on the 13th
negative-going clock edge.
SHORT CYCLE Input
The SHORT CYCLE input (Pin 21) permits the timing cycle shown
in Figure 7 to be terminated after any number of desired bits has
been converted, allowing somewhat shorter conversion times in
applications not requiring full 12-bit resolution. When 10-bit
resolution is desired, Pin 21 is connected to the BIT 11 output
(Pin 28). The conversion cycle then terminates, and the
STATUS flag resets after the BIT 10 decision (t10 + 40 ns in timing
diagram of Figure 7). Short cycle pin connections and
associated maximum 12-, 10-, and 8-bit conversion times are
summarized in Table 4. When 12-bit resolution is required,
SHORT CYCLE (Pin 21) is connected to 5V DIGITAL SUPPLY
(Pin 9).
INPUT SCALING
The ADADC80 input should be scaled as close to the maximum
input signal range as possible to use the maximum signal
resolution of the ADC. Connect the input signal as shown in
BIPOLAR
OFFSET OUT
ANALOG
GND
R2
5k
R1
5k
01
20
2
-00
8
FROM
DAC
TO SAR
COMPARATOR
6.3k
VREF
COMPARATOR IN
20V SPAN IN
10V SPAN IN 13
14
11
12
15
Figure 8. Input Scaling Circuit
Table 4. Short Cycle Connections
Connect SHORT CYCLE (Pin 21) to
Resolution (Bits)
(% FSR)
Maximum Conversion Time (μs)
STATUS Flag Reset
5V DIGITAL SUPPLY (Pin 9)
12
0.024
25
t12 + 40 ns
BIT 11 (Pin 28)
10
0.100
21
t10 + 40 ns
BIT 9 (Pin 30)
8
0.390
17
t8 + 40 ns
Table 5. Input Scaling Connections
Input Signal Range
Output Code
Connect BIPOLAR OFFSET OUT
(Pin 12) to
Connect 20V SPAN IN
(Pin 14) to
Connect Input Signal to
±10 V
COB or CTC
COMPARATOR IN (Pin 11)
Input Signal
20V SPAN IN (Pin 14)
±5 V
COB or CTC
COMPARATOR IN (Pin 11)
Open
10V SPAN IN (Pin 13)
±2.5 V
COB or CTC
COMPARATOR IN (Pin 11)
10V SPAN IN (Pin 13)
0 V to +5 V
CSB
ANALOG GND (Pin 15)
COMPARATOR IN (Pin 11)
10V SPAN IN (Pin 13)
0 V to +10 V
CSB
ANALOG GND (Pin 15)
Open
10V SPAN IN (Pin 13)
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