參數(shù)資料
型號(hào)： ADADC80-Z-12
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/16頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT INTEGRATED 32-CDIP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 40k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 800mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -25°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 32-CDIP（0.910"，23.12mm）
供應(yīng)商設(shè)備封裝： 32-CDIP 側(cè)面銅焊
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)單端，單極；2 個(gè)單端，雙極
ADADC80
Rev. E | Page 8 of 16
01
20
2-
00
7
THEORY OF OPERATION
Upon receipt of a CONVERT START command, the ADADC80
converts the voltage at its analog input into an equivalent 12-bit
binary number. This conversion is accomplished as follows:
1.
The 12-bit successive-approximation register (SAR) has its
12-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC.
2.
The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last).
3.
The decision to keep or reject each bit is then made at the
completion of each bit comparison period, depending on
the state of the comparator at that time.
TIMING
The timing diagram is shown in Figure 7. Receipt of a
CONVERT START signal sets the STATUS flag, indicating that
a conversion is in progress. This, in turn, removes the inhibit
applied to the gated clock, permitting it to run through 13 cycles.
All changes to the SAR parallel bit and to the STATUS bit are
initialized on the leading edge, and the gated clock inhibit
signal is removed on the trailing edge of the CONVERT START
signal. At time t0, BIT 1 is reset and BIT 2 to BIT 12 are set
unconditionally. At t1, the BIT 1 decision is made (keep) and
BIT 2 is unconditionally reset. At t2, the BIT 2 decision is made
(keep) and BIT 3 is reset unconditionally. This sequence
continues until the BIT 12 (LSB) decision (keep) is made at t12.
After a 40 ns delay period, the STATUS flag is reset, indicating
that the conversion is complete and the parallel output data is
valid. Resetting the STATUS flag restores the gated clock inhibit
signal, forcing the clock output to the Logic 0 state.
Parallel data bits become valid on the positive-going clock edge
(see Figure 7).
Incorporation of this 40 ns delay guarantees that the parallel
data is valid at the Logic l to Logic 0 transition of the STATUS
flag, permitting a parallel data transfer to be initiated by the
trailing edge of the STATUS signal.
MAXIMUM THROUGHPUT TIME
CONVERT
START1
INTERNAL
CLOCK
STATUS3
MSB
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
0
1
0
1
0
t0
t2
t1
t4
t3
t6
t5
t8
t7
t10
t9
t12
t11
CONVERSION TIME2
BIT 9
BIT 10
BIT 11
LSB
0
1
0
*
NOTES
1THE CONVERT START PULSE WIDTH IS 100ns MINIMUM AND MUST REMAIN LOW DURING A CONVERSION.
1THE CONVERSION IS INITIATED BY THE RISING EDGE OF THE CONVERT COMMAND.
225s FOR 12 BITS AND 21s FOR 10 BITS (MAXIMUM).
3t1 SHOWS THE MSB DECISION AND t11 SHOWS THE LSB DECISION 40ns PRIOR TO THE STATUS GOING LOW.
*BIT DECISIONS.
Figure 7. Timing Diagram (Binary Code 011001110110)
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