參數(shù)資料
型號: ADADC80-Z-12
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: IC ADC 12BIT INTEGRATED 32-CDIP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 40k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 800mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -25°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 32-CDIP(0.910",23.12mm)
供應(yīng)商設(shè)備封裝: 32-CDIP 側(cè)面銅焊
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極
ADADC80
Rev. E | Page 4 of 16
Parameter
Min
Typ
Max
Unit
INTERNAL REFERENCE VOLTAGE
+6.3 V
±10
± mV
Maximum External Current
(With No Degradation of Specifications)
1.5
mA
Temperature Coefficient of Drift5
±10
±20
ppm/°C
POWER REQUIREMENTS
Rated Voltages
±15, +5
V
Range for Rated Accuracy5
+5 V
+4.75
+5.25
V
±15 V
±14.0
±16.0
V
“Z” Models5, 9
+5 V
+4.75
+5.25
V
±15 V
±11.4
±16.0
V
Supply Drain
+15 V
+10
mA
15 V
20
mA
+5 V
+70
mA
TEMPERATURE RANGE
Specification
25
+85
°C
Operating (Derated Specifications)
55
+100
°C
Storage
55
+125
°C
1 DTL/TTL compatible, that is, Logic 0 = 0.8 V maximum and Logic 1 = 2.0 V minimum for digital inputs, Logic 0 = 0.4 V maximum and Logic 1 = 2.4 V minimum for digital outputs.
2 Adjustable to zero with external trimpots.
3 FSR means full-scale range, that is, unit connected for ±10 V range has +20 V FSR.
4 Error shown is the same as ± LSB maximum for resolution of analog-to-digital converter.
5 Guaranteed by design. Not production tested.
6 Conversion time with internal clock.
7 See Table 4. Complementary offset binary is COB, complementary straight binary is CSB, and complementary twos complement is CTC.
8 For conversion speeds specified.
9 For “Z” models, order ADADC80-Z-12.
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