參數(shù)資料
型號(hào)： AD9981KSTZ-95
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 10BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類(lèi)型： 表面貼裝
AD9981
Preliminary Technical Data
Rev. 0 | Page 38 of 44
POLARITY STATUS
0x25
7
Hsync0 Polarity
Indicates the polarity of the HSYNC0 input.
Table 62. Detected Hsync0 Polarity Results
Detect
Result
0
Hsync polarity is negative
1
Hsync polarity is positive
0x25
6
Hsync1 Polarity
Indicates the polarity of HSYNC1 input.
Table 63. Detected Hsync1 Polarity Results
Detect
Result
0
Hsync polarity is negative
1
Hsync polarity is positive
0x25
5
Vsync0 Polarity
Indicates the polarity of Vsync0 input.
Table 64. Detected Vsync0 Polarity Results
Detect
Result
0
Vsync polarity is negative
1
Vsync polarity is positive
0x25
4
Vsync1 Polarity
Indicates the polarity of Vsync1 input.
Table 65. Detected Vsync1 Polarity Results
Detect
Result
0
Vsync polarity is negative
1
Vsync polarity is positive
0x25
3
Coast Polarity
Indicates the polarity of the external Coast signal.
Table 66. Detected Coast Polarity Results
Detect
Result
0
Coast polarity is negative
1
Coast polarity is positive
0x25
2
Clamp Polarity
Indicates the polarity of the clamp signal.
Table 67. Detected Clamp Polarity Results
Detect
Result
0
Clamp polarity is negative
1
Clamp polarity is positive
0x25
1
Extraneous Pulses Detection
A second output from the Hsync filter, this status bit
tells whether extraneous pulses are present on the
incoming sync signal. Often extraneous pulses are
used for copy protection, so this status bit can be used
for this purpose.
Table 68. Equalization Pulse Detect Bit
Detect
Result
0
No equalization pulses detected during active
Hsync
1
Equalization pulses detected during active Hsync
HSYNC COUNT
0x26
7:0
Hsyncs/Vsync MSB
The eight MSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input. This is
useful for determining the mode and is an aid in
setting the PLL divide ratio.
0x27
7:4
Hsyncs/Vsync LSBs
The four LSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input.
Test Registers
0x28
7:0
Test Register 0
Must be written to 0xBF for proper operation.
0x29
7:0
Test Register 1
Must be written to 0x00 for proper operation.
0x2A
7:0
Test Register 2
Read-only bits for future use.
0x2B
7:0
Test Register 3
Read-only bits for future use.
0x2C
7:0
Test Register 4
Must be written to 0x00 for proper operation.
0x2C
4
Auto-Offset Hold
A bit for controlling whether the auto-offset function
runs continuously or runs once and holds the result.
Continuous updates are recommended because it
allows the AD9981 to compensate for drift-over time,
temperature, and so on. If one-time updates are
preferred, these should be performed every time the
part is powered up and when there is a mode change.
To do a one-time update, first auto-offset must be
enabled (0x1B, Bit 5). Next, this bit (auto-offset hold)
must be set to 1 to let the auto-offset function operate
and settle to a final value. Auto-offset hold should then
be set to 0 to hold the offset values that the auto
circuitry calculates. The AD9981’s auto-offset circuit’s
maxi-mum settle time is 10 updates. For example, if
the update frequency is set to once every 64 Hsyncs,
then the maximum settling time would be 640 Hsyncs
(10 × 64 Hsyncs).
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