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參數(shù)資料
| 型號： | AD9981KSTZ-95 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 10BIT ANALOG 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9981
Preliminary Technical Data
Rev. 0 | Page 30 of 44
PHASE ADJUST
0x04
7:3
Phase adjustment for the DLL to generate the ADC
clock. A 5-bit value that adjusts the sampling phase in
32 steps across one pixel time. Each step represents an
11.25° shift in sampling phase. The power up default
is 16.
INPUT GAIN
0x05
6:0
Red Channel Gain Adjust MSBs
The 7-Bit Red Channel Gain Control. The AD9981
can accommodate input signals with a full-scale range
of between 0.5 V and 1.0 V p-p. Setting the red gain to
511 corresponds to an input range of 1.0 V. A red gain
of 0 establishes an input range of 0.5 V. Note that
increasing red gain results in the picture having less
contrast (the input signal uses fewer of the available
converter codes). Values written to this register will
not be updated until the LSB register (R0x06) has also
been written. The power-up default is 1000000.
0x06
7:6
Red Channel Gain Adjust LSBs
The 2 Bit LSBs of the Red Channel Gain Control.
Along with the 7 MSBs of gain control in the previous
register, there are 9 bits of gain control. Default power
up value is 00.
0x07
6:0Green Channel Gain Adjust MSBs
The 7-Bit Green Channel Gain Control. See red
channel gain adjust above. Register update requires
writing 0x00 to Register 0x08.
0x08
7:6
Green Channel Gain Adjust LSBs
The 2-Bit LSBs of the Green Channel Gain Control.
Along with the 7 MSBs of gain control in the previous
register, there are 9 bits of gain control. Default power-
up value is 00.
0x09
6:0
Blue Channel Gain Adjust MSBs
The 7-Bit Blue Channel Gain Control. See red channel
gain adjust above. Register update requires writing
0x00 to Register 0x0A.
0x0A
7:6
Blue Channel Gain Adjust LSBs
The 2-Bit LSBs of the Blue Channel Gain Control.
Along with the 7 MSBs of gain control in the previous
register, there are 9 bits of gain control. Default power-
up value is 00.
INPUT OFFSET
0x0B
7:0
Red Channel Offset MSBs
The 8-Bit MSB of the Red Channel Offset Control.
Along with the 1 LSBs in the following register, there
are 11 bits of dc offset control in the red channel. The
offset control shifts the analog input, resulting in a
change in brightness. Note that the function of the
offset register depends on whether auto-offset is
enabled (Register 0x1B, Bit 5).
If auto-offset is disabled, the 9 bits of the offset reg-
isters (Bits [6:0] of the offset MSB register plus
Bits [7:6] of the following register) control the
absolute offset added to the channel (for the red
channel, Register 0x0B, Bits[6:0] plus Register 0x0C,
Bits [7:6]) control the absolute offset added to the
channel. The offset control provides a ±255 LSBs of
adjustment range, with 1 LSB of offset corresponding
to 1 LSB of output code.
If auto-offset is enabled, the 11-bit offset (comprised
of the 8 bits of the MSB register and Bits [7:5] of the
following register) determines the clamp target code.
The 11-bit offset consists of 1 sign bit plus 10 bits. If
the register is programmed to 530 DDR, then the
output code is equal to 530 DDR at the end of the
clamp period. Note that incrementing the offset
register setting by 1 LSB adds 1 LSB of offset,
regardless of the auto-offset setting. Values written to
this register are not updated until the LSB register
(Register 0x0C) has also been written.
0x0C
7:5
Red Channel Offset LSBs
The LSBs of the red channel offset control combine
with the 8 bits of MSB in the previous register to make
11 bits of offset control.
0x0D
7:0
Green Channel Offset MSBs
The 8-Bit Green Channel Offset Control. See red
channel offset (0x0B). Update of this register occurs
only when Register 0x0E is also written.
0x0E
7:5
Green Channel Offset LSBs
The LSBs of the green channel offset control combine
with the 8 bits of MSB in the previous register to make
11 bits of offset control.
0x0F
7:0
Blue Channel Offset MSBs
The 8-Bit Blue Channel Offset Control. See red
channel offset (0x0B). Update of this register occurs
only when Register 0x10 is also written.
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