參數(shù)資料
型號(hào): AD9913BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 32/32頁(yè)
文件大?。?/td> 0K
描述: IC DDS 10BIT DAC 250MSPS 32LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 10 b
主 fclk: 250MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 552 (CN2011-ZH PDF)
AD9913
Rev. A | Page 9 of 32
–50
–90
0
250
0
700
2-
0
33
SYSTEM CLOCK (MHz)
SF
D
R
(
d
B
c
)
–55
–60
–65
–70
–75
–80
–85
50
100
150
200
39.88%
26.58%
10.21%
Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)
–100
–170
10
100M
0
700
2-
0
42
FREQUENCY (MHz)
PH
A
SE
N
O
IS
E
(d
B
c
/H
z)
–110
–120
–130
–140
–150
–160
100
1k
10k
100k
1M
10M
92.3MHz
48.9MHz
23.1MHz
6.1MHz
Figure 11. Residual Phase Noise vs. fOUT (PLL Bypassed)
150
50
100
100M
FREQUENCY (MHz)
PH
A
SE
N
O
IS
E
(d
B
c
/H
z)
1k
10k
100k
1M
10M
60
70
80
90
100
110
120
130
140
99MHz
12.5MHz
49MHz
25MHz
07
00
2-
0
12
Figure 12. Absolute Phase Noise vs. fOUT Using the Internal PLL
(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)
–50
–90
00
0
700
2-
0
34
fOUT (% of System Clock)
SF
D
R
(
d
B
c
)
.45
–55
–60
–65
–70
–75
–80
–85
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
REFSPUR
PLL ×10
BYPASS
Figure 13. SFDR Without the Internal PLL
(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)
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