參數(shù)資料
型號: AD9913BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 30/32頁
文件大?。?/td> 0K
描述: IC DDS 10BIT DAC 250MSPS 32LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 10 b
主 fclk: 250MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
AD9913
Rev. A | Page 7 of 32
Pin No.
Mnemonic
I/O
Description
26
PWR_DWN_CTL
I
External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently
programmed power-down mode. See the Power-Down Features section for further details. If unused,
tie to ground.
27
IO_UPDATE
I
I/O Update; Digital Input. A high on this pin indicates a transfer of the contents of the I/O buffers to the
corresponding internal registers.
28
CS
I
Chip Select for Serial and Parallel Port. Digital input (active low). Bringing this pin low enables the
AD9913 to detect serial (SCLK) or parallel (PCLK) clock rising/falling edges. Bringing this pin high
causes the AD9913 to ignore input on the data pins.
29
SDIO(WR/RD)
I/O
Bidirectional Data Line for Serial Port Operation and Write/Read Enable for Parallel Port Operation.
30
SCLK/PCLK
I
Input Clock for Serial and Parallel Port.
31
ADR7/D7
I/O
Parallel Port Address Line 7 and Data Line 7.
32
ADR6/D6
I/O
Parallel Port Address Line 6 and Data Line 6.
33
Exposed Paddle
The EPAD should be soldered to ground.
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