參數(shù)資料
型號(hào)： AD9913BCPZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 0K
描述： IC DDS 10BIT DAC 250MSPS 32LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 10 b
主 fclk： 250MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
AD9913
Rev. A | Page 25 of 32
REGISTER UPDATE (I/O UPDATE)
Functionality of the I/O UPDATE and SYNC_CLK
Data from a write sequence is stored in a buffer register (data
inactive). An active register exists for every buffer register. The
I/O update signal and SYNC_CLK are used to transfer the
contents from the buffer register into the active register.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronously relative to the SYNC_CLK.
If the setup time between the two signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
constant propagation delay of phase offset changes via the SPI
or parallel port is desired, the setup time must be met,
otherwise, a time uncertainty of one SYNC_CLK period is
present.
The I/O_UPDATE is sampled by the SYNC_CLK. Therefore,
I/O_UPDATE must have a minimum pulse width greater than
one SYNC_CLK period.
The timing diagram shown in Figure 35 depicts how data in the
buffer is transferred to the active registers. An I/O_UPDATE is
not required for every register write, it can be sent after multiple
register writes.
SYNC_CLK
AB
DATA IN
ACTIVE REGISTER
DATA IN
BUFFER REGISTER
I/O_UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM
THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
0
700
2-
0
45
N – 1
N
N + 1
N
N + 1
N + 2
Figure 35. I/O Synchronization Timing Diagram
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AD9913BCPZ-REEL7 功能描述:IC DDS 250MSPS 10BIT ADC 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9913BCPZ-REEL71 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
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