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| 型號： | AD9895KBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標(biāo)準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 托盤 |
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REV. A
–34–
AD9891/AD9895
VDD
(INPUT)
SERIAL
WRITES
VD
(OUTPUT)
1 H
ODD FIELD
EVEN FIELD
SYNC
(INPUT)
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS
UPDATED AT VD/HD EDGE
H1/H3, RG, DCLK
H2/H4
tPWR
CLI
(INPUT)
HD
(OUTPUT)
1 V
Figure 42. Recommended Power-Up Sequence and Synchronization, Master Mode
POWER-UP AND SYNCHRONIZATION
Recommended Power-Up Sequence for Master Mode
When the AD9891/AD9895 are powered up, the following
sequence is recommended (refer to Figure 42 for each step).
1. Turn on power supplies for the AD9891/AD9895.
2. Apply the master clock input CLI.
3. Reset and initialize the internal AD9891/AD9895 Registers.
First, write a “1” to the SW_RESET Register (Addr x017)
followed by a “0” to the same register. Next, write
“110101” (53 decimal) to the INITIAL1 Register
(Addr x02B) followed by “000100” (4 decimal) to the
INTIAL2 Register (Addr x010). This sequence of writes
must always be done in the proper order:
Addr x017
Data 000001
Addr x017
Data 000000
Addr x02B
Data 110101
Addr x010
Data 000100
4. Configure the AD9891/AD9895 for Master Mode timing by
writing a “1” to the MASTER Register (Addr x0EB).
5. By default, the internal timing core is held in a reset state
with TGCORE_RSTB Register = “0.” Write a “1” to the
TGCORE_RSTB Register (Addr x029) to start the internal
timing core operation.
6. Write a “1” to the PREVENTUPDATE Register
(Addr x01B). This will prevent any updating of the serial
register data.
7. Write a “1” to the SYNCENABLE Register (Addr x024).
This will allow the external SYNC to be used.
8. Write a “1” to the SYNCSUSPEND Register (Addr x026).
This will cause the outputs to be suspended during the
SYNC operation (see Figure 43).
9. Write to desired registers to configure high speed timing,
horizontal timing, vertical timing, and shutter timing.
10. If SYNC is HIGH at power-up, then bring SYNC input
LOW. Also, SYNC may be held low from power-up.
11. Write a “1” to the OUT_CONT Register (Addr x018). This
will allow the outputs to become active after SYNC rising edge.
12. Write a “0” to the PREVENTUPDATE Register
(Addr x01B). This will allow the serial information to be up-
dated at the next VD/HD falling edge.
13. Bring SYNC back HIGH. This will cause the internal
counters to reset to “0” and start VD/HD operation.
VD/HD edge allows register updates to occur, including
OUT_CONT, which enables all clock outputs.
SYNC During Master Mode Operation
The SYNC input may be used any time during operation to
resync the AD9891/AD9895 counters with external timing, as
shown in Figure 43. The operation of the digital outputs may
be suspended during the SYNC operation by setting the
SYNCSUSPEND Register (Addr x026) to a “1.”
Synchronization in Slave Mode
When the AD9891/AD9895 is used in Slave Mode, the VD and
HD inputs are used to synchronize the internal counters. Fol-
lowing a falling edge of VD, there will be a latency of eight
master clock cycles (CLI) after the falling edge of HD until the
internal H-counter will be reset. The reset operation is shown in
Figure 44.
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