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| 型號： | AD9895KBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 托盤 |
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REV. A
–24–
AD9891/AD9895
Vertical Multiplier Mode
To generate very wide vertical timing pulses, a vertical region may
be configured into Multiplier Mode. This mode uses the vertical
sequence registers in a slightly different manner. Multiplier Mode
can be used to support unusual CCD timing requirements, such as
vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard sequence generation, but the length is
used differently. Instead of using the pixel counter (HD counter)
to specify the toggle position locations (VTPTOG1, 2, 3) of the
sequence, VTP length (VTPLEN) is multiplied by the
VTPTOG position to allow very long sequences to be generated.
To calculate the exact toggle position, counted in pixels after the
start position:
Multiplier Toggle Position VTPTOG VTPLEN
=×
Because the VTPTOG Register is multiplied by VTPLEN, the
resolution of the toggle position placement is reduced. If
VTPLEN = 4, the toggle position accuracy is now reduced to
4-pixel steps instead of single pixel steps. Table XII summarizes
how the Individual Vertical Sequence Registers are pro-
grammed for Multiplier Mode operation. Note that the bit
ranges for the VTPTOG and VTPREP Registers differ from the
normal operation shown in Table VII. In Multiplier Mode, the
VTPREP Register should always be programmed to the same
value as the highest toggle position register.
The example shown in Figure 27 illustrates this operation. The
first toggle position is 2 and the second toggle position is 9. In
Nonmultiplier Mode, this would cause the V-sequence to
toggle at pixel 2 and then pixel 9 within a single HD line. How-
ever, now toggle positions are multiplied by the VTPLEN = 4,
so the first toggle occurs at pixel count = 8, and the second toggle
occurs at pixel count = 36. Sweep Mode should be enabled to
allow the toggle positions to cross the HD line boundaries.
Frame Transfer CCD Mode
The AD9891/AD9895 may also be configured for use with frame
transfer CCDs. In Frame Transfer CCD (FTCCD) Mode,
an additional four vertical outputs are available for a total of
eight outputs (V1–V8). In this case, V1–V4 are used for clock-
ing the active image area, and V5–V8 are used for clocking the
storage area. In FTCCD Mode, the sequences assigned to the
V1–V4 outputs are duplicated at the V5–V8 outputs to allow the
storage area to be clocked along with the image area. Individual
masking of the V1–V4 and V5–V8 outputs allows for vertical
decimation techniques during transfer from the image to the
storage area. The additional outputs V5–V8 are available on four
of the sensor gate output pins, VSG1–VSG4. Figure 28 shows
an example of the eight V-clocks configured for use with a frame
transfer CCD.
V1–V4
HD
VTPLEN
MULTIPLIER MODE VERTICAL SEQUENCE PROPERTIES:
1: START POLARITY (ABOVE: STARTPOL = 0)
2: 1ST, 2ND, AND 3RD TOGGLE POSITIONS (ABOVE: VTPTOG1 = 2, VTPTOG2 = 9)
3: LENGTH OF VTP COUNTER (ABOVE: VTPLEN = 4). THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4: TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTPTOG
VTPLEN)
5: ENABLE SWEEP REGION ALLOWS THE COUNTERS TO CROSS THE HD BOUNDARIES
12
34
123412341234123412341234
1
2
34
1
2
3
4
1
2
3
4
START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT
PIXELS
1
234
5678
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
55
4
1
2
4
2
Figure 27. Example of Multiplier Region for Wide Vertical Pulse Timing
Table XII. Multiplier Mode and Sequence Register Parameters
Register
Length
Range
Description
MULTI
1b
HIGH/LOW
High Enables Multiplier Mode for Each Region 0–4
VTPPOL
1b
HIGH/LOW
Starting Polarity of Vertical Transfer Pulse for Each Sequence 0–11
VTPTOG1
12b
0–4095 Pixel Location
First Toggle Position for Each Sequence 0–11
VTPTOG2
12b
0–4095 Pixel Location
Second Toggle Position for Each Sequence 0–11
VTPTOG3
12b
0–4095 Pixel Location
Third Toggle Position for Each Sequence 0–7
VTPLEN
10b
0–1023 Pixels
“Multiplier” Factor for Repetition Counter
VTPREP
12b
0–4096
Should Be Programmed to the Same Value as the Highest Toggle Position
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