參數(shù)資料
型號(hào)： AD9878BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/36頁
文件大?。?/td> 0K
描述： IC FRONT-END MIXED-SGNL 100-LQFP
產(chǎn)品變化通告： AD9878BSTZ Discontinuation 21/Nov/2011
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 673mW
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 3.3V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
AD9878
Rev. A | Page 17 of 36
Setting this bit to 0 (default) configures the serial interface to be
compatible with AD8321/AD8323/AD8328 variable cable gain
amplifiers. Setting this bit to 1 configures the serial interface to be
compatible with AD8322/AD8327 variable cable gain amplifiers.
Bit 5: Profile Select
The AD9878 quadrature digital upconverter can store two
preconfigured modulation modes, called profiles. Each profile
defines a transmit FTW, cable-driver amplifier gain setting, and
DAC gain setting. The profile select bit or PROFILE pin programs
the current register profile to be used. If the PROFILE pin is used
to switch between profiles, the profile select bit should be set to 0
and tied low.
REGISTERS 0x10 THROUGH 0x17—
BURST PARAMETER
Tx Frequency Tuning Words
The FTW determines the DDS-generated carrier frequency (fC)
and is formed via a concatenation of register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB, and Bit 0 is the LSB. The carrier frequency equation is
as follows:
() 26
2
SYSCLK
C
f
FTW
f
×
=
Where
2000
x
0
and
,
<
×
=
FTW
f
M
f
OSCIN
SYSCLK
.
Changes to FTW bytes take effect immediately.
Cable-Driver Gain Control
The AD9878 has a 3-pin interface to the AD832x family of
programmable gain cable-driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9878. In its
default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13
and Register 0x17 determine the 8-bit word sent over the CA
interface, according to the specifications in Table 6. Bits [3:0] of
Register 0x13 and Register 0x17 determine the fine gain setting
of the DAC output, according to specifications in Table 7.
Table 6. Cable-Driver Gain Control
Bits [7:4]
CA Interface Transmit Word
0000
0000 0000 (default)
0001
0000 0001
0010
0000 0010
0011
0000 0100
0100
0000 1000
0101
0001 0000
0110
0010 0000
0111
0100 0000
1000
1000 0000
Table 7. DAC Output Fine Gain Setting
Bits [3:0]
DAC Fine Gain (dB)
0000
0.0 (default)
0001
0.5
0010
1.0
0011
1.5
…
1110
7.0
1111
7.5
New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
value is 0x00 (lowest gain).
The formula for the combined output-level calculation of
AD9878 fine gain and AD8327 or AD8322 coarse gain is:
()
(
)
() 19
2
0
9878
8327
+
=
coarse
fine
V
()
(
)
(
) 14
2
0
9878
8322
+
=
coarse
fine
V
where:
fine
is the decimal value of Bits [3:0].
coarse
is the decimal value of Bits [7:4].
V9878(0)
is the level at AD9878 output in dBmV for fine = 0.
V8327
is the level at output of AD8327 in dBmV.
V8322
is the level at output of AD8322 in dBmV.
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