參數(shù)資料
型號(hào)： AD9878BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 0K
描述： IC FRONT-END MIXED-SGNL 100-LQFP
產(chǎn)品變化通告： AD9878BSTZ Discontinuation 21/Nov/2011
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 673mW
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 3.3V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤(pán)
AD9878
Rev. A | Page 26 of 36
POWER-UP SEQUENCE
Upon initial power-up, the RESET pin should be held low until the
power supply is stable (see Figure 30). Once RESET is deasserted,
the AD9878 can be programmed over the serial port. The on-
chip PLL requires a maximum of 1 ms after the rising edge of
RESET or a change of the multiplier factor (M) to completely
settle. It is recommended that the PWRDN pin is held low during
the reset and PLL settling time. Changes to ADC clock select
(Register 0x08) or System Clock Divider N (Register 0x01) should
be programmed before the rising edge of PWRDN. Once the PLL
is frequency locked and after the PWRDN pin is brought high,
transmit data can be sent reliably. If the PWRDN pin cannot be
held low throughout the reset and PLL settling time period,
the power-down digital Tx bit, or the PWRDN pin, should be
pulsed after the PLL has settled. This ensures correct transmit
filter initialization.
03277-
014
VS
1ms MIN.
5MCLK MIN.
RESET
PWRDN
Figure 30. Power-Up Sequence for Tx Data Path
RESET
To initiate a hardware reset, the RESET pin should be held low
for at least 100 ns. All internally generated clocks, except REFCLK,
stop during reset. The rising edge of RESET resets the PLL clock
multiplier and reinitializes the programmable registers to their
default values. The same sequence as described in the Power-Up
Sequence section should be followed after a reset or change in M.
A software reset (writing 1 into Bit 5 of Register 0x00) is func-
tionally equivalent to a hardware reset, but does not force
Register 0x00 to its default value.
TRANSMIT POWER-DOWN
A low level on the PWRDN pin stops all clocks linked to the
digital transmit data path and resets the CIC filter. Deasserting
PWRDN reactivates all clocks. The CIC filter is held in a reset
state for 80 MCLK cycles after the rising edge of PWRDN to
allow for flushing of the half-band filters with new input data.
Transmit data bursts should be padded with at least 20 symbols
of null data directly before the PWRDN pin is deasserted.
Immediately after the PWRDN pin is deasserted, the transmit
burst should start with a minimum of 20 null data symbols (see
Figure 31). This avoids unintended DAC output samples caused
by the transmit path latency and filter settling time.
Software power-down digital Tx (Bit 5 in Register 0x02) is func-
tionally equivalent to the hardware PWRDN pin and takes effect
immediately after the last register bit is written over the serial port.
PWRDN
TxIQ
TxSYNC
20 NULL SYMBOLS
DATA SYMBOLS
20 NULL SYMBOLS
0
00
5MCLK MIN.
03277-015
Figure 31. Timing Sequence to Flush Tx Data Path
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