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參數(shù)資料
| 型號： | AD9878BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRONT-END MIXED-SGNL 100-LQFP |
| 產(chǎn)品變化通告： | AD9878BSTZ Discontinuation 21/Nov/2011 |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 673mW |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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AD9878
Rev. A | Page 23 of 36
Tx THROUGHPUT AND LATENCY
Data inputs affect the output fairly quickly, but remain effective
due to the AD9878 filter characteristics. Data transmit latency
through the AD9878 is easiest to describe in terms of fSYSCLK clock
cycles (4 × fMCLK). The numbers provided indicate the number of
fSYSCLK cycles before the AD9878 output responds to a change in
the input.
Latency of I/Q data from the time it enters the data assembler
(AD9878 input) to the time of DAC output is 119 fSYSCLK clock
cycles (29.75 fMCLK cycles). DC values applied to the data assembler
input take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to
propagate and settle at the DAC output.
Frequency hopping is accomplished via changing the PROFILE
input pin. The time required to switch from one frequency to
another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).
DAC
A 12-bit digital-to-analog converter (DAC) is used to convert the
digitally processed waveform into an analog signal. The worst-
case spurious signals due to the DAC are the harmonics of the
fundamental signal and their aliases (see the Analog Devices
DDS tutorial at www.analog.com/dds). The conversion process
produces aliased components of the fundamental signal at
(
).3
,
2
,
1
=
±
×
n
f
n
CARRIER
SYSCLK
These are typically filtered
with an external RLC filter at the DAC output. It is important
for this analog filter to have a sufficiently flat gain and linear
phase response across the bandwidth of interest to avoid
modulation impairments. A relatively inexpensive seventh-
order, elliptical, low-pass filter is sufficient to suppress the
aliased components for HFC network applications.
The AD9878 provides true and complement current outputs. The
full-scale output current is set by the RSET resistor at Pin 49 and
the DAC gain register. Assuming maximum DAC gain, the value
of RSET for a full-scale IOUT is determined using the equation:
OUT
DACRSET
SET
I
V
R
4
.
39
32
=
For example, if a full-scale output current of 20 mA is desired,
then RSET = (39.4/0.02), or approximately 2 k.
The following equation calculates the full-scale output current,
including the programmable DAC gain control:
() 20
5
.
0
5
.
7
10
4
.
39
GAIN
N
SET
OUT
R
I
+
×
=
where NGAIN is the value of DAC fine gain control [3:0].
The full-scale output current range of the AD9878 is 4 to
20 mA. Full-scale output currents outside this range degrade
SFDR performance. SFDR is also slightly affected by output
matching—that is, the two outputs should be terminated equally
for best SFDR performance. The output load should be located
as close as possible to the AD9878 package to minimize stray
capacitance and inductance. The load can be a simple resistor to
ground, an op amp current-to-voltage converter, or a transformer-
coupled circuit. It is best not to directly drive a highly reactive
load, such as an LC filter. Driving an LC filter without a
transformer requires that the filter be doubly terminated for
best performance—that is, both the filter input and output should
be resistively terminated with the appropriate values. The parallel
combination of the two terminations determines the load that
the AD9878 sees for signals within the filter pass band. For
example, a 50 terminated input/output low-pass filter looks
like a 25 load to the AD9878. The output compliance voltage
of the AD9878 is 0.5 V to +1.5 V. Any signal developed at the
DAC output should not exceed 1.5 V; otherwise, signal distortion
as 0.5 V without damage or signal distortion. The AD9878 true
and complement outputs can be differentially combined for
common-mode rejection using a broadband 1:1 transformer.
Using a grounded center tap results in signals at the AD9878 DAC
output pins that are symmetrical about ground. As previously
mentioned, by differentially combining the two signals, the user
can provide some degree of common-mode signal rejection.
A differential combiner can consist of a transformer or an
op amp. The object is to combine or amplify the difference
between only two signals and to reject any common—usually
undesirable—characteristics, such as 60 Hz hum or clock
feedthrough, that is equally present on both signals.
AD832x
AD9878
VARIABLE GAIN
CABLE DRIVER
AMPLIFIER
3
Tx
CA
DAC
75
LOW-PASS
FILTER
CA_EN
CA_DATA
CA_CLK
03277-011
Figure 27. Cable Amplifier Connection
Connecting the AD9878 true and complement outputs to the
differential inputs of the programmable gain cable drivers
AD8321/AD8323 or AD8322/AD8327 (see Figure 27)
provides an optimized solution for the standard compliant
cable modem upstream channel. The cable driver’s gain
can be programmed through a direct 3-wire interface
using the AD9878 profile registers.
PROGRAMMING THE AD8321/AD8323 OR
AD8322/AD8327/AD8238 CABLE-DRIVER
AMPLIFIERS
amplifiers via the AD9878 cable amplifier control interface. Two
(one per profile) 8-bit registers within the AD9878 store the gain
value to be written to the serial 3-wire port. Typically, either the
AD8321/AD8323 or AD8322/AD8327 variable gain cable
amplifiers are connected to the chip’s 3-wire cable amplifier
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| AD9879BSZ | 功能描述:IC PROCESSOR FRONT END 100MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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