AD9830–SPECIFICATIONS1 Parameter AD9830A Units Test Conditions/Comments SIGNAL DAC SPECIFICATIONS R" />
參數(shù)資料
型號(hào)： AD9830ASTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 0K
描述： IC DDS 10BIT 50MHZ CMOS 48-TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 10 b
主 fclk： 50MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： EVAL-AD9830EBZ-ND - BOARD EVALUATION AD9830
–2–
AD9830–SPECIFICATIONS1
Parameter
AD9830A
Units
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate (fMAX)
50
MSPS max
IOUT Full Scale
20
mA max
Output Compliance
1
V max
DC Accuracy
Integral Nonlinearity
±1
LSB typ
Differential Nonlinearity
±0.5
LSB typ
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal-to-Noise Ratio
50
dB min
fMCLK = fMAX , fOUT = 2 MHz
Total Harmonic Distortion
–53
dBc max
fMCLK = fMAX , fOUT = 2 MHz
Spurious Free Dynamic Range (SFDR)
3
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
Narrow Band
(
±50 kHz)
–72
dBc min
(
±200 kHz)
–68
dBc min
Wide Band (
±2 MHz)
–50
dBc min
Clock Feedthrough
–55
dBc typ
Wake Up Time
1
ms typ
Power-Down Option
Yes
VOLTAGE REFERENCE
Internal Reference @ +25
°C
1.21
Volts typ
TMIN to TMAX
1.21
± 7%
Volts min/max
REFIN Input Impedance
10
M
typ
Reference TC
100
ppm/
°C typ
REFOUT Impedance
300
typ
LOGIC INPUTS
VINH, Input High Voltage
VDD–0.9
V min
VINL, Input Low Voltage
0.9
V max
IINH, Input Current
10
A max
CIN, Input Capacitance
10
pF max
POWER SUPPLIES
fOUT = 2 MHz
AVDD
4.75/5.25
V min/V max
DVDD
4.75/5.25
V min/V max
IAA
25
mA max
IDD
6 + 0.5/MHz
mA typ
IAA + IDD
4
60
mA max
Low Power Sleep Mode
5
0.25
mA typ
1 M
Resistor Tied Between
1
mA max
REFOUT and AGND
(VDD = +5 V
5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT;
RSET = 1 k ; RLOAD = 51
for IOUT and IOUT unless otherwise noted)
NOTES
1Operating temperature range is as follows: A Version: –40
°C to +85°C.
2All dynamic specifications are measured using IOUT. 100% production tested.
3f
MCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz.
4Measured with the digital inputs static and equal to 0 V or DVDD.
5The Low Power Sleep Mode current is 2 mA typically when a 1 M
resistor is
not tied from REFOUT to AGND.
The AD9830 is tested with a capacitive load of 50 pF. The part can be operated
with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 10 MHz output signal will be attenuated by 3 dB when the
load capacitance equals 250 pF.
Specifications subject to change without notice.
FULL-SCALE
CONTROL
10-BIT
DAC
SIN
ROM
ON-BOARD
REFERENCE
12
REFOUT
REFIN
FS
ADJUST
COMP
IOUT
51
50pF
51
50pF
AVDD
RSET
1k
10nF
Figure 1. Test Circuit with Which Specifications Are
Tested
REV. B
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