Figure 17. f
參數(shù)資料
型號(hào): AD9830ASTZ
廠商: Analog Devices Inc
文件頁數(shù): 16/16頁
文件大?。?/td> 0K
描述: IC DDS 10BIT 50MHZ CMOS 48-TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 10 b
主 fclk: 50MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: EVAL-AD9830EBZ-ND - BOARD EVALUATION AD9830
AD9830
–9–
RBW 1kHz
VBW 3kHz
ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz
STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency
Word = 547AE148
Register
Size
Description
FREQ0 REG
32 Bits
Frequency Register 0. This defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
FREQ1 REG
32 Bits
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
PHASE0 REG
12 Bits
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
PHASE1 REG
12 Bits
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
PHASE2 REG
12 Bits
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
PHASE3 REG
12 Bits
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
Figure 18. AD9830 Control Registers
A2
A1
A0
Destination Register
0
FREQ0 REG 16 LSBs
0
1
FREQ0 REG 16 MSBs
0
1
0
FREQ1 REG 16 LSBs
0
1
FREQ1 REG 16 MSBs
1
0
PHASE0 REG
1
0
1
PHASE1 REG
1
0
PHASE2 REG
1
PHASE3 REG
Figure 19. Addressing the Control Registers
D15
D0
MSB
LSB
Figure 20. Frequency Register Bits
D15
D14 D13 D12 D11
D0
X
XXXMSB
LSB
X = Don't Care
Figure 21. Phase Register Bits
REV. B
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