參數(shù)資料
型號(hào)： AD9782
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing
中文描述： 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號(hào)處理
文件頁數(shù)： 8/52頁
文件大小： 1619K
代理商： AD9782
AD9782
Preliminary Technical Data
ANALOG
Table 5. Analog Pin Function Descriptions
Pin No.
59
60
70, 71
61
62, 79
63, 78
64, 77
65, 76
66, 75
67, 74
68, 73
69, 72
Rev. PrC | Page 8 of 52
Mnemonic
REFIO
FSADJ
IOUTB, IOUTA
DNC
ADVDD
ADGND
ACVDD
ACGND
AVDD2
AGND2
AVDD1
AGND1
Direction
A
A
A
Description
Reference.
Full-Scale Adjust.
Differential DAC Output Currents.
Do not connect.
Analog Domain Digital Content 2.5 V.
Analog Domain Digital Content 0 V.
Analog Domain Clock Content 2.5 V.
Analog Domain Clock Content 0 V.
Analog Domain Clock Switching 3.3 V.
Analog Domain Switching 0 V.
Analog Domain Quiet 3.3 V.
Analog Domain Quiet 0 V.
DATA
Table 6. Data Pin Function Descriptions
Pin No.
Mnemonic
10–15, 18–24,
27–29
Direction
I
Description
Input Data Port One.
ONEPORT
02h[6]
0
1
Mode
Latched Data Routed for 1 Channel Processing.
Latched Data Demultiplexed by IQSEL and Routed for Interleaved
I/Q Processing.
IQPOL
02h[1]
P2B15
Mode (IQPOL == 0)
X
X
Latched data routed to Q channel bit 15(MSB)
processing.
0
0
Latched data on data port one routed to Q
channel processing.
0
1
Latched data on data port one routed to I
channel processing.
1
0
Latched data on data port one routed to I
channel processing.
1
1
Latched data on data port one routed to Q
channel processing.
P1B15–P1B0
ONEPORT
02h[6]
0
IQSEL/
1
1
1
32
IQSEL/P2B15
I
1
ONEPORT
02h[6]
0
1
Input Data Port Two Bits 13–0.
Latched data routed for Q channel Bit 14 processing.
Pin configured for output of clock at twice the channel data route.
33
ONEPORTCLK/P2B14
I/O
34, 37–43,
46–51
30
9, 17, 26,
36, 44, 52
8, 16, 25,
35, 45, 53
P2B13–P2B0
I
DRVDD
DVDD
Digital Output Pin Supply, 2.5 V or 3.3 V.
Digital Domain 2.5 V.
DGND
Digital Domain 0 V.
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