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參數(shù)資料
| 型號： | AD9782 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing |
| 中文描述： | 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理 |
| 文件頁數(shù)： | 25/52頁 |
| 文件大?。?/td> | 1619K |
| 代理商： | AD9782 |
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Preliminary Technical Data
AD9782
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the
AD9782’s inputs on every other rising edge of DACCLK, as
shown in Figure 40 and Figure 41. With DCLKPOL = 1, as
shown in Figure 40, the latching edge of DACCLK is the rising
DCLKPOL = 0, as in Figure 41, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising
edge of DATACLK. The setup and hold time values are identical
to those in Figure 37 and Figure 38.
Rev. PrC | Page 25 of 52
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 39 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input runs
at 4× or 8× the speed of the DATACLK output. The data is
latched in on a rising edge of DACCLK, similar to the 2×
interpolation mode. However, the latching edge is every fourth
edge in 4× interpolation mode and every eighth edge in the 8×
interpolation mode. Again, similar to operation in the 2×
interpolation mode, with DCLKPOL = 1, the latching edge of
DACCLK is the rising edge that occurs just before the falling
edge of DATACLK. With DCLKPOL = 0, the latching edge of
DACCLK is the rising edge that occurs just before the rising
edge of DATACLK. The setup and hold time values are identical
to those in 1× and 2× interpolation
0
Figure 39.
0
DACCLK
IN
DATACLK
OUT
DATA
t
D
= 5ns TYP
t
S
= –0.5ns TYP
t
H
= 2.9ns TYP
Figure 40. Data Timing, DLL Off, 2× Interpolation, DCLKPOL = 1
0
DACCLK
IN
DATACLK
OUT
DATA
t
D
= 6ns TYP
t
S
= –0.5ns TYP
t
H
= 2.9ns TYP
Figure 41. Data Timing, DLL Off, 2× Interpolation, DCLKPOL = 0
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