參數(shù)資料
型號： AD9782
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing
中文描述： 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理
文件頁數(shù)： 20/52頁
文件大小： 1619K
代理商： AD9782
AD9782
Preliminary Technical Data
Table 13.
DATA(02)
DATAFMT
Rev. PrC | Page 20 of 52
Bit
7
Direction
I
Default
0
Description
0: Twos complement data format
1: Unsigned binary input data format
0: I and Q input data onto ports one and two respectively
1: I and Q input data interleaved onto port one
0: DATACLK pin 12 mA drive strength
1: DATACLK pin 24 mA drive strength
0: Input data latched on DATACLK rising edge
1: Input data latched on DATACLK falling edge
0: With PLOCKEXT off, DATACLK pin inputs channel data rate or modulator synchronizer clock
1: With PLOCKEXT off, DATACLK pin outputs channel data rate or modulator synchronizer clock
0: With PLOCKEXT off, and DATACLK pin as input, DATACLK clock recovery off
1: With PLOCKEXT off, and DATACLK pin as input, DATACLK clock recovery on
0: In one port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data into Q channel
1: In one port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data into Q channel
0: Gray decoder off
1: Gray decoder on
ONEPORT
6
I
0
DCLKSTR
5
I
0
DCLKPOL
4
I
0
DCLKEXT
3
I
0
DCLKCRC
2
I
0
IQPOL
1
I
0
GRAYDIN
0
I
0
Table 14.
MODULATE(03)
CHANNEL
Bit
7
Direction
I
Default
0
Description
MODDUAL
03h [5]
0
0
1
1
1: With MODDUAL on, Hilbert transform on
0: Modulator uses a single channel
1: Modulator uses both I and Q channels
0: With MODDUAL on, lower sideband rejected
1: With MODDUAL on, upper sideband rejected
00: No modulation
01: f
S
/2 modulation
10: f
S
/4 modulation
11: f
S
/8 modulation
CHANNEL
03h[7]
0
1
0
1
I channel processing routed to DAC
Q channel processing routed to DAC
Modulator real output routed to DAC
Modulator imaginary output routed to DAC
HILBERT
MODDUAL
6
5
I
I
0
0
SIDEBAND
4
I
0
MOD[1:0]
[3:2]
I
00
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