參數(shù)資料
型號: AD9782
廠商: Analog Devices, Inc.
英文描述: 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing
中文描述: 12位,200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理
文件頁數(shù): 7/52頁
文件大小: 1619K
代理商: AD9782
Preliminary Technical Data
AD9782
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrC | Page 7 of 52
80 79 78 77 76
71 70 69 68 67 66 65
75 74 73 72
64 63 62 61
16
1
2
3
4
5
6
7
8
9
10
11
13
14
15
12
17
18
20
19
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P
PIN 1
IDENTIFIER
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC = NO CONNECT
N
A
A
A
A
A
A
A
A
I
I
A
A
A
A
A
A
A
A
D
CLKVDD
LPF
CLKVDD
CLKGND
CLK+
CLK–
CLKGND
DGND
DVDD
P1B15
P1B14
P1B13
P1B12
P1B11
P1B10
DGND
DVDD
P1B9
P1B8
P1B7
FSADJ
REFIO
RESET
CSB
SCLK
SDIO
SDO
DGND
DVDD
P2B0
P2B1
P2B2
P2B3
P2B4
P2B5
DGND
DVDD
P2B6
P2B7
P2B8
P
P
P
D
D
P
P
P
D
I
O
P
D
D
D
AD9782
TOP VIEW
(Not to Scale)
P
P
P
P
0
Figure 2. Pin Configuration
CLOCK
Table 4. Clock Pin Function Descriptions
Pin
No.
Mnemonic
5, 6
CLK+, CLK–
2
LPF
31
DATACLK/PLL_LOCK
Direction
I
I/O
I/O
Description
Differential Clock Input.
PLL Loop Filter.
PLOCKEXT
04h[0]
0
DCLKEXT
02h[3]
0
Mode
Pin configured for input of channel data rate or synchronizer clock.
Internal clock synchronizer may be turned on or off with DCLKCRC
(02h[2]).
Pin configured for output of channel data rate or synchronizer clock
Internal Clock PLL Status Output:
0: Internal clock PLL is not locked.
1: Internal clock PLL is locked.
0
1
1
X
1, 3
4, 7
CLKVDD
CLKGND
Clock Domain 2.5 V.
Clock Domain 0 V.
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