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參數(shù)資料
| 型號： | AD9753 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit,300 MSPS High Speed T×DAC+TM D/A Converter(300MSPS,超高速,單通道12位D/A轉(zhuǎn)換器) |
| 中文描述： | 12位，300 MSPS的高速厚×援商標D / A轉(zhuǎn)換（300MSPS，超高速，單通道12位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 152K |
| 代理商： | AD9753 |
DATA
TECHNCAL
10-22
μ
F
T ANT .
CERAMIC
8 REV. PrA
Due to the internal PLL, the time at which the data in
the port 1 and port 2 input latches is written to the
DAC latch is independent of the duty cycle of CLK .
PLL DISABLED MODE
When PLLVDD is grounded, the PLL is disabled. An
external
clock must now drive the CLK inputs at the
desired DAC output update data rate. T he speed and
timing of the data present at input ports 1 and 2 is now
dependent on whether or not the AD9753 is interleav-
ing the digital input data, or only responding to data
on a single port. Figure 8 is a functional block
diagram of the AD9753 clock control circuitry with
the PL L disabled.
DIV0 and DIV1 no longer control the PLL, but are
used to set the control on the input mux for either
interleaving or non-interleaving the input data. T he
different modes for states of DIV0 and DIV1 are given
in T able II.
INTERLEAVING DATA WITH PLL DISABLED
T he relationship between the internal and external
clocks in this mode is shown in Figure 9. A clock at
the output update data rate (2
×
the input data rate)
must be applied to the CLK inputs. T he input latches
are now updated by the internally generated 1
×
clock,
while the DAC latch is updated by the external 2
×
clock. A delayed version of the 1
×
clock is available at
the LOCK pin. Updates to the data at input ports 1
and 2 should be synchronized to the rising edge of the
external 2
×
clock which corresponds to the risng edge
of the 1
×
internal clock as shown in Figure 9. T o
ensure this synchronization, a logic “1” should be
momentarily applied to the RESET pin on power up,
before CLK is applied.
AD9753
DAT A IN
PORT 2
data y
CLK
tLPW
tPD
1/2 cycle + tPD
IOUT A
OR
IOUT B
data y
data x
DAT A IN
PORT 1
tS
tH
data x
Figure 6. DAC Input Timing Requirements with PLL Active
Figure 6a.
Figure 7. LC Network for Power Filtering
Table II, Input Mode for DIV0, DIV1 Levels
with PLL Disabled
Input Mode
Port 1
Port 2
NOT ALLOWED
DIV1
0
0
1
1
DIV0
0
1
0
1
Table I, CLK rates for DIV0, DIV1 levels
with PLL active
CLK freq
DIV1
50-150 MHz
0
25-100 MHz
0
12.5-50 MHz
1
6.25-25 MHz
1
DIV0
0
1
0
1
Range Controller
÷
1
÷
2
÷
4
÷
8
Figure 8. AD9753 Clock Circuitry with PLL Disabled
CLK IN+
CLK IN-
DIFF T O
SINGLE
ENDED AMP
T O
INPUT
LAT CHES
CLOCK
LOGIC
(
÷
1 OR
÷
2)
PLLVDD
LOCK
RESET
T O DAC
LAT CH
DIV0DIV1
T O
INT ERNAL
MUX
DAT A IN
PORT 1
PORT 2
DAT A W
DAT A Y
IOUT A
OR
IOUT B
CLK
DAT A X
DAT A Z
DAT A W DAT A X
DAT A Y
DAT A Z
X X X
T T L/CMOS
LOGIC
CIRCUIT S
2.7 to 3.6V
POWER SUPPLY
FERRIT E BEADS
CLK COM
100
μ
F
ELECT .
0.1
μ
F
CLK VDD
Figure 6b.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9753AST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel 制造商:Analog Devices 功能描述:IC 12-BIT DAC |
| AD9753ASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel |
| AD9753ASTZ | 功能描述:IC DAC 12BIT 300MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9753ASTZRL | 功能描述:IC DAC 12BIT 300MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9753-EB | 功能描述:BOARD EVAL FOR AD9753 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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