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參數(shù)資料
| 型號(hào)： | AD9753 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit,300 MSPS High Speed T×DAC+TM D/A Converter(300MSPS,超高速,單通道12位D/A轉(zhuǎn)換器) |
| 中文描述： | 12位，300 MSPS的高速厚×援商標(biāo)D / A轉(zhuǎn)換（300MSPS，超高速，單通道12位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | AD9753 |
PRELMNARY
All of the current sources are switched to one or the
other of the two outputs (i.e., IOUT A or IOUT B) via
PMOS differential current switches. T he switches are
based on a new architecture that drastically improves
distortion performance. T his new switch architecture
reduces various timing errors and provides matching
complementary drive signals to the inputs of the
differential current switches.
T he analog and digital sections of the AD9753 have
separate power supply inputs (i.e., AVDD and DVDD)
that can operate independently over a 2.7 volt to 3.6
Volt range. T he digital section, which is capable of
operating at a 300 MSPS clock rate, consists of edge-
triggered latches and segment decoding logic circuitry.
T he analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V
bandgap voltage reference and a reference control
amplifier.
T he full-scale output current is regulated by the
reference control amplifier and can be set from 2 mA
to 20 mA via an external resistor, R
SET
. T he external
resistor, in combination with both the reference control
amplifier and voltage reference V
REFIO
, sets the refer-
TECHNCAL
6 REV. PrA
FUNCTIONAL DESCRIPTION
Figure 2 shows a simplified block diagram of the
AD9753. T he AD9753 consists of a PMOS current
source array capable of providing up to 20ma of full-
scale current, I
. T he array is divided into 31 equal
sources that make up the five most significant bits
(MSB’s). T he next four bits, or middle bits, consist of
15 equal current sources whose value is 1/16th of an
MSB current source. T he remaining LSBs are a binary
weighted fraction of the middle bit current sources.
Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances dynamic
performance for multitone or low amplitude signals and
helps maintain the DAC’s high output impedance (i.e.,
>100K
).
AD9753
ence current I
REF
, which is replicated to the segmented
current sources with the proper scaling factor. T he
full-scale current, I
OUT FS
, is thirty-two times the value of
I
REF
.
REFERENCE OPERATION
T he AD9753 contains an internal 1.20 V bandgap
reference. T his can be easily overdriven by an external
reference with no effect on performance. REFIO serves
as either an inputor outputdepending on whether the
internal or an external reference is used. T o use the
internal reference, simply decouple the REFIO pin to
ACOM with a 0.1
μ
F capacitor. T he internal reference
voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an
external buffer amplifier with an input bias current less
than 100nA should be used. An example of the use of
the internal reference is given in Figure 3.
An external reference can be applied to REFIO as
shown in Figure 4. T he external reference may provide
either a fixed reference voltage to enhance accuracy
and drift performance or a varying reference voltage
for gain control. Note that the 0.1 μF compensation
capacitor is not required since the internal reference is
overdriven, and the relatively high input impedance of
REFIO minimizes any loading of the external refer-
ence.
REFERENCE CONTROL AMPLIFIER
T he AD9753 also contains an internal control ampli-
fier that is used to regulate the DAC’s full-scale output
current, I
OUT FS
. T he control amplifier is configured as
a voltage to current converter as shown in Figure 3, so
that its current output, I
REF
, is determined by the ratio
of V
REFIO
and an external resistor, R
SET
, as stated in
Equation 4. I
REF
is applied to the segmented current
sources with the proper scaling factor to set I
OUT FS
as
stated in Equation 3.
T he control amplifier allows a wide (10:1) adjustment
span of I
OUT FS
over a 2 mA to 20 mA range by setting
IREF between 62.5 μA and 625 μA. T he wide adjust-
ment span of I
OUT FS
provides several application
Figure 2. Simplified Block Diagram
IOUT A
IOUT B
SEGMENT ED
SWIT CHES FOR
DB0 T O DB11
DAC
AVDD
ACOM
Port 1 latch
Port 2 latch
2-1 mux
DAC LAT CH
PMOS CURRENT
SOURCE ARRAY
1.2V REF
+
-
REFIO
FSADJ
DCOM
DVDD
PLL CIRCUIT RY
CLK +
CLK -
PLLVDD
CLK VDD
CLK COM
RESET
LPF
LOCK
RSET
2K
+2.7 to +3.6V
0.1
μ
f
RLOAD
50
RLOAD
50
VoutA
VoutB
Vdiff=VoutA-VoutB
DB0-DB11
DIGIT AL DAT A INPUT S
DB0-DB11
AD9753
DIV0 DIV1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9753AST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel 制造商:Analog Devices 功能描述:IC 12-BIT DAC |
| AD9753ASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel |
| AD9753ASTZ | 功能描述:IC DAC 12BIT 300MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9753ASTZRL | 功能描述:IC DAC 12BIT 300MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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