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參數(shù)資料
| 型號(hào)： | AD9753 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit,300 MSPS High Speed T×DAC+TM D/A Converter(300MSPS,超高速,單通道12位D/A轉(zhuǎn)換器) |
| 中文描述： | 12位，300 MSPS的高速厚×援商標(biāo)D / A轉(zhuǎn)換（300MSPS，超高速，單通道12位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | AD9753 |
7 REV. PrA
DATA
Figure 4. External Reference Configuration
TECHNCAL
short propagation delay.
Following the rising edge, at a time equal to half the
period of CLK , the data in the port 1 latch will be
written to the DAC output latch, again with a corre-
sponding change in the DAC output.
On the next rising edge of CLK , the cycle begins
again with the two input port latches being updated,
and the DAC output latch being updated with the
current data in the port 2 input latch.
AD9753
benefits. T he first benefit relates directly to the power
dissipation of the AD9753, which is proportional to
I
OUT FS
(refer to the POWER DISSIPAT ION section).
T he second benefit relates to the 20 dB adjustment,
which is useful for system gain control purposes.
T he small signal bandwidth of the reference control
amplifier is approximately 500K Hz and can be used
for low frequency small signal multiplying applica-
tions.
PLL CLOCK MULTIPLIER OPERATION
T he Phase Locked Loop (PLL) is intrinsic to the
operation of the AD9753 in that it produces the
necessary internally synchronized 2
×
clock for the edge
triggered latches, multiplexer and DAC.
With PLLVDD connected to its supply voltage, the
AD9753 is in PLL ACT IVE mode. Fig 5 shows a
functional block diagram of the AD9753 clock control
circuitry with PLL active. T he circuitry consists of a
phase detector, charge pump, voltage controlled
oscillator (VCO), input data rate range control, clock
logic circuitry and control input/outputs. T he
÷
2 logic
in the feedback loop allows the PLL to generate the 2
×
clock needed for the DAC output latch.
Figure 6 defines the input and output timing for the
AD9753 with the PLL active. CLK in Figure 6
represents the clock which is generated external to the
AD9753 which also updates the input data at ports 1
and 2. CLK may be applied as a single ended signal by
tying CLK - to mid supply and applying CLK to
CLK +, or as a differential signal applied to CLK + and
C L K -.
RESET has no purpose when using the internal PLL
and should be grounded. When the AD9753 is in PLL
ACT IVE mode, LOCK is the output of the internal
phase detector. When locked, the lock output in this
mode will be a logic “1”.
T ypically, the VCO can generate outputs of 100 to 400
MHz. T he range control is used to keep the VCO
operating within its designed range, while allowing
input clocks as low as 6.25 MHz. With the PLL
active, logic levels at DIV0 and DIV1 determine the
divide ratio of the range controller. T able I gives the
frequency range of the input clock for the different
states of DIV0 and DIV1.
A 392
resistor and 1.0
μ
f capacitor connected in
series from LPF to PLLVDD are required to optimize
istics of the PLL. T o obtain optimum noise and
distortion performance, PLLVDD should be set to a
voltage level similar to DVDD.
SNR is partly a function of the jitter generated by the
clock circuitry. As a result, any noise on PLLVDD or
CLK VDD may decrease the SNR at the output of the
DAC. T o minimize this potential problem, PL L VDD
and CLK VDD can be connected to DVDD using an
LC filter network similar to that shown in Figure 7.
In PLL ACT IVE mode, port 1 and port 2 input
latches are updated on the rising edge of CLK . On the
same rising edge, data which was previously stored in
the input port 2 latch is written to the DAC output
latch. T he DAC output will update accordingly after a
Figure 5. AD9753 Clock Circuitry with PLL Active
Figure 3. Internal Reference Configuration
optional
external
reference
buffer
additional
external
load
0.1
μ
F
2K
REFIO
FSADJ
1.2V
ref
AVDD
current
source
array
AD9753
reference
section
IREF
AVDD
External
Reference
2K
REFIO
FSADJ
1.2V
ref
AVDD
current
source
array
AD9753
reference
section
IREF
CLK +
CLK -
DIFF T O
SINGLE
ENDED AMP
T O INPUT
LAT CHES
÷
2
PHASE
DET ECT OR
CHARGE
PUMP
VCO
LPF
PLLVDD
+2.7 to +3.6v
392
1.0
μ
F
LOCK
RANGE CONT ROL
(
÷1, 2, 4, 8
)
T O DAC
LAT CH
DIV0
DIV1
CLK VDD
(+2.7 to +3.6v)
CLK COM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9753AST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel 制造商:Analog Devices 功能描述:IC 12-BIT DAC |
| AD9753ASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel |
| AD9753ASTZ | 功能描述:IC DAC 12BIT 300MSPS 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱(chēng):MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9753ASTZRL | 功能描述:IC DAC 12BIT 300MSPS 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:* |
| AD9753-EB | 功能描述:BOARD EVAL FOR AD9753 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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