參數(shù)資料
型號(hào)： AD9717-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 46/80頁(yè)
文件大小： 0K
描述： ADC 14BIT DUAL 40LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9717
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 50 of 80
Two registers are assigned to each DAC with 10 bits for the actual
DAC current to be generated, a 3-bit offset (and gain) adjust-
ment, a 2-bit current range adjustment, and an enable/disable
bit. Setting the QAUXOFS (Register 0x0A, Bits[4:2]) and
IAUXOFS (Register 0x0C, Bits[4:2]) bits to all 1s disables the
respective op amp and routes the DAC current directly to the
respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is
especially useful when the loads to be driven are beyond the
limited capability of the on-chip amplifier.
When not enabled (QAUXEN or IAUXEN = 0), the respective
DAC output is in open circuit.
DAC-TO-MODULATOR INTERFACING
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 108
and Figure 109, with the series resistor value chosen to give an
appropriate adjustment range. Figure 108 also shows external
load resistors in use. Often, the input common-mode voltage for
the modulator is much higher than the output compliance range
of the DAC, so that ac coupling or a dc level shift is necessary. If
the required common-mode input voltage on the quadrature
modulator matches that of the DAC, the dc blocking capacitors in
Figure 108 can be removed and the on-chip resistors can be
connected.
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
AD9714/AD9715/
AD9716/AD9717
AUX DAC
OPTIONAL
PASSIVE
FILTERING
MODULATOR
V+
QUADRATURE
MODULATOR
I OR Q
INPUTS
499
0.1F
5k
TO
100k
0.1F
499
07
26
5-
1
66
Figure 108. Typical Use of Auxiliary DACs and External Components for
Coupling to Quadrature Modulators
Figure 109 shows a greatly simplified circuit that takes full
advantage of the internal components supplied in the DAC. A
low-pass or band-pass passive filter is recommended when
spurious signals from the DAC (distortion and DAC images)
at the quadrature modulator inputs can affect the system
performance. In the example shown in Figure 109, the filter
must be able to pass dc to properly bias the modulator. Placing
the filter at the location shown in Figure 108 and Figure 109
allows easy design of the filter because the source and load imped-
ances can easily be designed close to 500 Ω for a 2 mA full-scale
output. Once the resistance at the modulator inputs is known,
the user can easily look up the range of input offsets that may be
encountered and compute a value for the series resistor on the
AUXDAC output.
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
AD9714/AD9715/
AD9716/AD9717
AUX DAC
OPTIONAL
LOW-PASS
FILTERING
ADL537x
FAMILY
I OR Q
INPUTS
50k
500
1k
0
72
65
-1
67
Figure 109. Simplified DC Coupling to Quadrature Modulator ADL537x
Family or Equivalent Is Enabled By Using Internal Components
CORRECTING FOR NONIDEAL PERFORMANCE OF
QUADRATURE MODULATORS ON THE IF-TO-RF
CONVERSION
Analog quadrature modulators make it very easy to realize
single sideband radios. However, there are several nonideal
aspects of quadrature modulator performance. Among these
analog degradations are gain mismatch and LO feedthrough.
Gain Mismatch
The gain in the real and imaginary signal paths of the quad-
rature modulator may not be matched perfectly. This leads
to less than optimal image rejection because the cancellation of
the negative frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well
as coupling from its LO port to the signal inputs. These can lead
to a significant spectral spur at the frequency of the quadrature
modulator LO.
The AD9714/AD9715/AD9716/AD9717 have the capability
to correct for both of these analog degradations. However,
understand that these degradations drift over temperature;
therefore, if close to optimal single sideband performance
is desired, a scheme for sensing these degradations over
temperature and correcting them may be necessary.
I/Q-CHANNEL GAIN MATCHING
Fine gain matching is achieved by adjusting the values in the
DAC fine gain adjustment registers. For the I DAC, these values
are in the I DAC gain register (Register 0x03). For the Q DAC,
these values are in the Q DAC gain register (Register 0x06). These
are 6-bit values that cover ±2% of full scale. To perform gain
compensation starting from the default values of zero, raise the
value of one of these registers a few steps until it can be deter-
mined if the amplitude of the unwanted image is increased or
decreased. If the unwanted image increases in amplitude, remove
the step and try the same adjustment on the other DAC control
register. Iterate register changes until the rejection cannot be
improved further. If the fine gain adjustment range is not sufficient
to find a null (that is, the register goes full scale with no null
apparent), adjust the course gain settings of the two DACs
accordingly and try again. Variations on this simple method
are possible.
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