參數(shù)資料
型號: AD9717-DPG2-EBZ
廠商: Analog Devices Inc
文件頁數(shù): 23/80頁
文件大小: 0K
描述: ADC 14BIT DUAL 40LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC®
DAC 的數(shù)量: 2
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9717
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 3 of 80
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Changes to Figure 1...........................................................................4
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Table 1 Conditions ............................................................................5
Changes to Table 1 ............................................................................5
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Table 2 Conditions ............................................................................7
Changed DVDD = 3.3 V to DVDD = 1.8 V, and DVDDIO = 1.8 V
to DVDDIO = 3.3 V, Table 3 Conditions .......................................8
Changed DVDD = 3.3 V to DVDD = 1.8 V, CVDD = 3.3 V to
CVDD = 1.8 V, Table 4 Conditions.................................................8
Changes to Table 5 and Table 6 .......................................................9
Changes to Figure 2 and Table 7 ...................................................10
Changes to Figure 3 and Table 8 ...................................................12
Changes to Figure 4 and Table 9 ...................................................14
Changes to Table 10 ........................................................................16
Changes to Typical Performance Characteristics Section .........18
Changes to Figure 84 and Theory of Operation Section ...........32
Added Figure 85 to Figure 88; Renumbered Sequentially .........34
Changes to Pin Mode Section........................................................35
Changes to Table 13 ........................................................................36
Changes to Table 14 ........................................................................37
Changes to Digital Interface Operation Section and Figure 89 to
Figure 93...........................................................................................40
Changes to Digital Data Latching and Retimer Block Section,
Figure 94, and Retimer Section .....................................................41
Changes to Estimating the Overall DAC Pipeline Delay
Section ..............................................................................................42
Added Reference Operation Section, Figure 96,
Recommendations When Using an External Reference Section,
and Reference Control Amplifier Section....................................43
Added Table 17; Renumbered Sequentially.................................43
Added DAC Transfer Function Section and Analog Output
Section ..............................................................................................44
Changes to Figure 99 and Figure 100 ...........................................46
Changes to Auxiliary DACs Section and Figure 107..................49
Changes to DAC-to-Modulator Interfacing Section and
Figure 108.........................................................................................49
Changes to Figure 108 and Figure 109 .........................................50
Added Evaluation Board Schematics and Artwork Section, and
Figure 112 to Figure 134.................................................................53
Added Bill of Materials Section and Table 18 .............................76
8/08—Revision 0: Initial Version
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