參數(shù)資料
型號: AD9649BCPZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 22/32頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS 32LFCSP
標準包裝: 1,500
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應商設備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
AD9649
Rev. 0 | Page 29 of
32
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
USR2 (Register 0x101)
Bit 3—Enable GCLK Detect
Normally set high, Bit 3 enables a circuit that detects encode
rates below ~5 MSPS. When a low encode rate is detected, an
internal oscillator, GCLK, is enabled, ensuring the proper oper-
ation of several circuits. If set low, the detector is disabled.
Bit 2—Run GCLK
Bit 2 enables the GCLK oscillator. For some applications with
encode rates below 10 MSPS, it may be preferable to set this bit
high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
Bit 0 can be set high to disable the internal 30 kΩ pull-down on
the SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
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