參數(shù)資料
型號: AD9649BCPZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 20/32頁
文件大小: 0K
描述: IC ADC 14BIT 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
AD9649
Rev. 0 | Page 27 of
32
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr.
(Hex)
Register Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Def.
Value
(Hex)
Default
Notes/
Comments
Chip configuration registers
0x00
SPI port
configuration
0
LSB first
Soft
reset
1
Soft
reset
LSB first
0
0x18
The nibbles are
mirrored so that
LSB or MSB first
mode registers
correctly, regard-
less of shift
mode.
0x01
Chip ID
8-bit chip ID, Bits[7:0]
AD9649 = 0x6F
Read
only
Unique chip ID
used to differen-
tiate devices;
read only.
0x02
Chip grade
Open
Speed grade ID, Bits[6:4]
(identify device variants of chip ID)
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Open
Read
only
Unique speed
grade ID used to
differentiate
devices; read
only.
Device transfer registers
0xFF
Transfer
Open
Transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Program registers
0x08
Modes
External
Pin 23
MODE
input
enable
External Pin 23
function when high
00 = full power-down
01 = standby
10 = normal mode,
output disabled
11 = normal mode,
output enabled
Open
00 = chip run
01 = full power-down
10 = standby
11 = chip wide
digital reset
0x00
Determines
various generic
modes of chip
operation.
0x0B
Clock divide
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