參數(shù)資料
型號： AD9634BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 20/32頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS 32-LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 340mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 2 單端，1 個(gè)差分
AD9634
Rev. 0 | Page 27 of 32
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
Nibbles are
mirrored so
that LSB-
first mode
or MSB-first
mode is set
correctly,
regardless
of shift
mode.
0x01
Chip ID
8-bit chip ID[7:0], AD9634 = 0x87 (default)
0x87
Read only.
0x02
Chip grade
Open
Speed grade ID;
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
Open
Speed
grade ID
used to
differentiate
devices;
read only.
Transfer Register
0xFF
Transfer
Open
Transfer
0x00
Synchro-
nously
transfers
data from
the master
shift
register to
the slave.
ADC Function Registers
0x08
Power modes
Open
Internal power-down mode
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
0x00
Determines
various
generic
modes of
chip
operation.
0x09
Global clock
Open
Duty cycle
stabilizer
(default)
0x01
0x0B
Clock divide
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Clock divide
values other
than 000
auto-
matically
cause the
duty cycle
stabilizer to
become
active.
0x0D
Test mode
0 = contin-
uous/
repeat
pattern
1 = single
pattern
then zeros
Open
Reset PN
long gen
Reset PN
short gen
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
0x00
When this
register is
set, the test
data is
placed on
the output
pins in
place of
normal
data.
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