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| 型號： | AD9634BCPZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 340mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 單端，1 個差分 |
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AD9634
Rev. 0 | Page 22 of 32
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
excellent jitter performance.
100
0.1F
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDS DRIVER
ADC
099
96
-05
2
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9634 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1, the DCS is enabled by default on
power-up.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9634 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate may change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS loop
is relocked to the input signal. During the time that the loop is
not locked, the DCS loop is bypassed, and internal device timing
is dependent on the duty cycle of the input clock signal. In such
applications, it may be appropriate to disable the duty cycle
stabilizer. In all other applications, enabling the DCS circuit is
recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
SNRHF = 10 log[(2π × fIN × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
80
75
70
65
60
55
50
1
10
100
1000
S
NR
(
d
BF
S
)
INPUT FREQUENCY (MHz)
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
09
996
-05
4
Figure 56. AD9634-250 SNR vs. Input Frequency and Jitter
In cases where aperture jitter may affect the dynamic range of the
AD9634, treat the clock input as an analog signal. In addition,
use separate power supplies for the clock drivers and the ADC
output driver to avoid modulating the clock signal with digital
noise. Low jitter, crystal controlled oscillators provide the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), it should be retimed by the
original clock during the last step.
Refer to AN-501 Application Note, Aperture Uncertainty and ADC
System Performance, and AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter, for more
information about jitter performance as it relates to ADCs.
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| AD9634BCPZ-210 | 制造商:Analog Devices 功能描述:12 BIT 210 MSPS ADC - Trays 制造商:Analog Devices 功能描述:IC ADC 12BIT 210MSPS 32-LFCSP 制造商:Analog Devices 功能描述:ADC 12BIT 210MSPS 32LFCSP 制造商:Analog Devices 功能描述:IC ADC 12 bit 210 MSPS Ser 制造商:Analog Devices 功能描述:ADC, 12BIT, 210MSPS, 32LFCSP 制造商:Analog Devices 功能描述:12 Bit 210 Msps ADC 制造商:Analog Devices 功能描述:CONVERTER - ADC |
| AD9634BCPZ-250 | 制造商:Analog Devices 功能描述:12 BIT 250 MSPS ADC - Trays 制造商:Analog Devices 功能描述:IC ADC 12BIT 250MSPS 32-LFCSP 制造商:Analog Devices 功能描述:IC ADC 12 bit 250 MSPS Ser 制造商:Analog Devices 功能描述:ADC 12BIT 250MSPS 32LFCSP 制造商:Analog Devices 功能描述:ADC, 12BIT, 250MSPS, 32LFCSP 制造商:Analog Devices 功能描述:12 Bit 250 Msps ADC 制造商:Analog Devices 功能描述:CONVERTER - ADC |
| AD9634BCPZRL7-170 | 功能描述:IC ADC 12BIT SRL 170MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9634BCPZRL7-210 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 Bit 210 Msps ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9634BCPZRL7-250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 Bit 250 Msps ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
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