參數(shù)資料
型號: AD9634BCPZ-170
廠商: Analog Devices Inc
文件頁數(shù): 1/32頁
文件大小: 0K
描述: IC ADC 12BIT 170MSPS 32-LFCSP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 340mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-WQ(5x5)
包裝: 托盤
輸入數(shù)目和類型: 2 單端,1 個差分
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2011 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 87 dBc at 185 MHz AIN and 250 MSPS
150.6 dBFS/Hz input noise at 185 MHz, 1 dBFS AIN and
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 350 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
12
REFERENCE
SERIAL PORT
SCLK
SDIO
CSB
CLK+
CLK–
1-TO-8
CLOCK DIVIDER
AD9634
VIN+
D0±/D1±
D10±/D11±
DCO±
OR±
VIN–
VCM
AVDD
AGND
DRVDD
.
PARALLEL
DDR LVDS
AND
DRIVERS
PIPELINE
12-BIT
ADC
099
96-
001
Figure 1.
GENERAL DESCRIPTION
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The AD9634 is designed to
support communications applications where low cost, small size,
wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit
LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a
3-wire, SPI-compatible serial interface.
The AD9634 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of 40°C to +85°C. This product
is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4. 3-pin, 1.8 V SPI port for register programming and readback.
5. Pin compatibility with the AD9642, allowing a simple
migration up to 14 bits, and with the AD6672.
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