參數(shù)資料
型號(hào)： AD9558BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 81/104頁(yè)
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 64LFCSP
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
標(biāo)準(zhǔn)包裝： 750
類(lèi)型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 4:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9558
Data Sheet
Rev. B | Page 78 of 104
Table 61. History Mode
Address
Bits
Bit Name
Description
0x0316
[7:5]
Reserved
Reserved.
4
Single sample fallback
Controls holdover history. If tuning word history is not available for the reference
that was active just prior to holdover, then:
0 (default) = uses the free run frequency tuning word register value.
1 = uses the last tuning word from the DPLL.
3
Persistent history
Controls holdover history initialization. When switching to a new reference:
0 (default) = clears the tuning word history.
1 = retain the previous tuning word history.
[2:0]
Incremental average
History mode value from 0 to 7 (default: 0).
When set to non-zero, causes the first history accumulation to update prior to the
first complete averaging period. After the first full interval, updates occur only at the
full period.
0 (default) = update only after the full interval has elapsed.
1 = update at 1/2 the full interval.
2 = update at 1/4 and 1/2 of the full interval.
3 = update at 1/8, 1/4, and 1/2 of the full interval.
...
7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval.
Table 62. Base Digital Loop Filter with High Phase Margin (PM = 88.5°, BW = 0.1 Hz, Third Pole Frequency = 10 Hz, N1 = 1)1
Address
Bits
Bit Name
Description
0x0317
[7:0]
HPM Alpha-0 linear
Alpha-0 coefficient linear bits[7:0]. Default: 0x8C
0x0318
[7:0]
Alpha-0 coefficient linear bits[15:8]
0x0319
7
Reserved
[6:0]
HPM Alpha-1 exponent
Alpha-1 coefficient exponent bits[6:0]
0x031A
[7:0]
HPM Beta-0 linear
Beta-0 coefficient linear bits[7:0]
0x031B
[7:0]
Beta-0 coefficient linear bits[15:8]
0x031C
7
Reserved
[6:0]
HPM Beta-1 exponent
Beta-1 coefficient exponent bits[6:0]
0x031D
[7:0]
HPM Gamma-0 linear
Gamma-0 coefficient linear bits[7:0]
0x031E
[7:0]
Gamma-0 coefficient linear bits[15:8]
0x031F
7
Reserved
[6:0]
HPM Gamma-1 exponent
Gamma-1 coefficient exponent bits[6:0]
0x0320
[7:0]
HPM Delta-0 linear
Delta-0 coefficient linear bits[7:0]
0x0321
[7:0]
Delta-0 coefficient linear bits[15:8]
0x0322
7
Reserved
[6:0]
HPM Delta-1 exponent
Delta-1 coefficient exponent bits[6:0]
1
Note that the base digital loop filter coefficients (α, β, γ, and δ) have the following general form: x(2y), where x is the linear component and y is the exponential
component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 ≤ x ≤ 1. The exponential component (y) is a signed integer.
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AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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