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參數(shù)資料
型號(hào)： AD9558BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/104頁(yè)
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 64LFCSP
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 4:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9558
Rev. B | Page 29 of 104
THEORY OF OPERATION
09758-
135
SPI/I2C
SERIAL PORT
EEPROM
REF MONITORING
AUTOMATIC
SWITCHING
÷N1
÷N2
÷N3
÷2
÷M1
OUT11
OUT21
MAX 1.25GHz
÷M2
×2
LF
PFD/CP
RF
DIVIDER 1
÷3 TO ÷11
XO OR XTAL
XO FREQUENCIES
10MHz TO 180MHz
XTAL: 10MHz TO 50MHz
RF
DIVIDER 2
÷3 TO ÷11
FRAME SYNC PULSE
FRAME SYNC
MODE ONLY
OUTPUT PLL (APLL)
FRAC1/
MOD1
17-BIT
INTEGER
24b/24b
RESOLUTION
DIGITAL PLL (DPLL)
2kHz TO 8kHz FRAME SYNC SIGNAL
÷2
REGISTER
SPACE
2kHz
T
O
1.
25G
Hz
R DIVIDER
(20-BIT)
SYNC
RESET
PINCONTROL
M0 M1 M2 M3
IRQ
SPI/I2C
DIGITAL
LOOP
FILTER
TUNING
WORD
CLAMP
AND
HISTORY
FREE RUN
TW
APLL
STATUS
LF_VCO2
PFD/CP
LF
DPFD
30-BIT
NCO
ROM
AND
FSM
MULTIFUNCTION I/O PINS
(CONTROL AND STATUS
READBACK)
SYSTEM
CLOCK
MULTIPLIER
M4 M5 M6 M7
÷2
AD9558
÷M0
÷M0 TO ÷M3b ARE
10-BIT INTEGER
DIVIDERS
1OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz
OUT0
OUT01
÷M3
OUT41
÷M3b
OUT51
×2
OUT31
REFC
REFD
÷2
REFA
REFB
1
3.35GHz
TO
4.05GHz
Figure 35. Detailed Block Diagram
OVERVIEW
The AD9558 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference, but
with jitter characteristics that are governed by the system clock,
the DCO, and the output PLL (APLL). The AD9558 supports
up to four reference inputs and input frequencies ranging from
2 kHz to 1250 MHz. The core of this product is a digital phase-
locked loop (DPLL). The DPLL has a programmable digital loop
filter that greatly reduces jitter that is transferred from the active
reference to the output. The AD9558 supports both manual and
automatic holdover. While in holdover, the AD9558 continues to
provide an output as long as the system clock is present. The
holdover output frequency is a time average of the output
frequency history just prior to the transition to the holdover
condition. The device offers manual and automatic reference
switchover capability if the active reference is degraded or fails
completely. The AD9558 also has adaptive clocking capability
that allows the DPLL divider ratios to be changed while the DPLL
is locked.
The AD9558 has a system clock multiplier, a digital PLL (DPLL),
and an analog PLL (APLL). The input signal goes first to the DPLL,
which performs the jitter cleaning and most of the frequency
translation. The DPLL features a 30-bit digitally controlled
oscillator (DCO) output that generates a signal in the 175 MHz
to 200 MHz range. The DPLL output goes to an analog integer-N
PLL (APLL), which multiplies the signal up to the 3.35 GHz to
4.05 GHz range. That signal is then sent to the clock distribution
section, which has two divide-by-3 to divide-by-11 RF dividers
that are cascaded with 10-bit integer (divide-by-1 to divide-by-
1024) channel dividers.
The XOA and XOB pins provide the input for the system clock.
These pins accept a reference clock in the 10 MHz to 600 MHz
range, or a 10 MHz to 50 MHz crystal connected directly across
the XOA and XOB pins. The system clock provides the clocks to
the frequency monitors, the DPLL, and internal switching logic.
The AD9558 has six output drivers, arranged into four channels.
Each channel has a dedicated 10-bit programmable post divider.
Channel 0 and Channel 3 have one driver each, and Channel 1
and Channel 2 have two drivers each. Each driver is programmable
either as a single differential or dual single-ended CMOS output.
The clock distribution section operates at up to 1250 MHz.
In differential mode, the output drivers run on a 1.8 V power
supply to offer very high performance with minimal power
consumption. There are two differential modes: LVDS and 1.8 V
HSTL. In 1.8 V HSTL mode, the voltage swing is compatible
with LVPECL. If LVPECL signal levels are required, the designer
can ac-couple the AD9558 output and use Thevenin-equivalent
termination at the destination to drive the LVPECL inputs.
In single-ended mode, each differential output driver can
operate as two single-ended CMOS outputs. OUT0 and OUT5
support either 1.8 V or 3.3 V CMOS operation. OUT1 through
OUT4 support only 1.8 V operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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