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| 型號： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設(shè)計資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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AD9548
Data Sheet
Rev. E | Page 28 of 112
DQ
R
0
1
EN
FAULTED
VALID
FORCE VALIDATION
TIMEOUT
REF FAULT
REF MONITOR
BYPASS
REF MONITOR
OVERRIDE
REGISTER CONTROL BITS
REFERENCE VALIDATION LOGIC
(8 COPIES, 1 PER REFERENCE INPUT)
REFERENCE
MONITOR
R
VALIDATION TIMER
TIMEOUT
08
02
2-
01
0
Figure 35. Reference Validation Override
The main feature to note is that any time faulted = 1, the output
latch is reset, which forces valid = 0 (indicating an invalid reference)
regardless of the state of any other signal. Under the default
condition (that is, all three control bits are 0), the reference
monitor is the primary source of the validation process. This is
because, under the default condition, the ref fault signal from
the reference monitor is identically equal to the faulted signal.
The function of the faulted signal is fourfold.
Any time faulted = 1, then valid = 0, regardless of the state
of any other control signal. Therefore, faulted = 1 indicates
an invalid reference.
Any time the faulted signal transitions from 0 to 1 (that is,
from nonfaulted to faulted), the validation timer is
momentarily reset, which means that, when it is enabled, it
must exhaust its full counting sequence before it expires.
When faulted = 0 (that is, the reference is not faulted), the
validation timer is allowed to perform its timing sequence.
When faulted = 1 (that is, the reference is faulted), the
validation timer is reset and halted.
The faulted signal passes through an inverter, converting it
to a nonfaulted signal, which appears at the input of the
valid latch. This allows the valid latch to capture the state
of the nonfaulted signal when the validation timer expires.
The ref monitor bypass control bit enables bypassing of the ref
fault signal generated by the reference monitor. When ref
monitor bypass = 1, the state of the faulted signal is dictated by
the ref monitor override control bit. This is useful when the
user relies on an external reference monitor rather than the
internal monitor resident in the device. The user programs the
ref monitor override bit based on the status of the external
monitor. On the other hand, when ref monitor bypass = 0, the
ref monitor override control bit allows the user to manually test
the operation of both the valid latch and the validation timer. In
this case, the user relies on the signal generated by the internal
reference monitor (ref fault) but uses the ref monitor override
bit to emulate a faulted reference. That is, when ref monitor
override = 1, then faulted = 1, but when ref monitor override = 0,
then faulted = ref fault.
In addition, the user has the ability to emulate a timeout of the
validation timer via the appropriate force validation timeout
control bit in Register 0x0A0E. Writing a Logic 1 to any of these
autoclearing bits triggers the valid latch, which is identically
equivalent to a timeout of the validation timer.
REFERENCE PROFILES
The AD9548 has eight independent profile registers. A profile
register contains 50 bytes that establish a particular set of device
parameters. Each of the eight input references can be assigned
to any one of the eight profiles (that is, more than one reference
can be assigned to the same profile). The profiles allow the user
to prescribe the specific device functionality that should take
effect when one of the input references (assigned to the profile)
becomes the active reference. Each profile register has the same
format and stores the following device parameters:
Reference priority
Reference period value (in femtoseconds)
Inner tolerance value (1/tolerance)
Outer tolerance value (1/tolerance)
Validation timer value (milliseconds)
Redetect timer value (milliseconds)
Digital loop filter coefficients
Reference prescaler setting (R-divider)
Feedback divider settings (S, U, and V)
DPLL phase lock detector threshold level
DPLL phase lock detector fill rate
DPLL phase lock detector drain rate
DPLL frequency lock detector threshold level
DPLL frequency lock detector fill rate
DPLL frequency lock detector drain rate
Reference-to-Profile Assignment Control
The user can manually assign a reference to a profile or let the
device make the assignment automatically. The manual reference
profile selection register (Address 0x0503 to Address 0x0506) is
where the user programs whether a reference-to-profile
assignment is manual or automatic. The manual reference
profile selection register is a 4-byte register partitioned into
eight half bytes (or nibbles). The eight nibbles form a one-to-one
correspondence with the eight reference inputs: one nibble for
REF A, the next for REF AA, and so on. For a reference configured
as a differential input, however, the device ignores the nibble
associated with the two-letter input. For example, if the B
reference is differential, then only the REFB nibble matters (the
device ignores the REFBB nibble).
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