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| 型號： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設(shè)計資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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AD9548
Data Sheet
Rev. E | Page 100 of 112
Table 138. IRQ Monitor for Reference Inputs
Address
Bits
Bit Name
Description
0x0D06
[7]
Ref AA new profile
Indicates that Ref AA has switched to a new profile
[6]
Ref AA validated
Indicates that Ref AA has been validated
[5]
Ref AA fault cleared
Indicates that Ref AA has been cleared of a previous fault
[4]
Ref AA fault
Indicates that Ref AA has been faulted
[3]
Ref A new profile
Indicates that Ref A has switched to a new profile
[2]
Ref A validated
Indicates that Ref A has been validated
[1]
Ref A fault cleared
Indicates that Ref A has been cleared of a previous fault
[0]
Ref A fault
Indicates that Ref A has been faulted
0x0D07
[7]
Ref BB new profile
Indicates that Ref BB has switched to a new profile
[6]
Ref BB validated
Indicates that Ref BB has been validated
[5]
Ref BB fault cleared
Indicates that Ref BB has been cleared of a previous fault
[4]
Ref BB fault
Indicates that Ref BB has been faulted
[3]
Ref B new profile
Indicates that Ref B has switched to a new profile
[2]
Ref B validated
Indicates that Ref B has been validated
[1]
Ref B fault cleared
Indicates that Ref B has been cleared of a previous fault
[0]
Ref B fault
Indicates that Ref B has been faulted
0x0D08
[7]
Ref CC new profile
Indicates that Ref CC has switched to a new profile
[6]
Ref CC validated
Indicates that Ref CC has been validated
[5]
Ref CC fault cleared
Indicates that Ref CC has been cleared of a previous fault
[4]
Ref CC fault
Indicates that Ref CC has been faulted
[3]
Ref C new profile
Indicates that Ref C has switched to a new profile
[2]
Ref C validated
Indicates that Ref C has been validated
[1]
Ref C fault cleared
Indicates that Ref C has been cleared of a previous fault
[0]
Ref C fault
Indicates that Ref C has been faulted
0x0D09
[7]
Ref DD new profile
Indicates that Ref DD has switched to a new profile
[6]
Ref DD validated
Indicates that Ref DD has been validated
[5]
Ref DD fault cleared
Indicates that Ref DD has been cleared of a previous fault
[4]
Ref DD fault
Indicates that Ref DD has been faulted
[3]
Ref D new profile
Indicates that Ref D has switched to a new profile
[2]
Ref D validated
Indicates that Ref D has been validated
[1]
Ref D fault cleared
Indicates that Ref D has been cleared of a previous fault
[0]
Ref D fault
Indicates that Ref D has been faulted
Table 139. DPLL Status
Address
Bits
Bit Name
Description
0x0D0A
[7]
Offset slew limiting
The current closed-loop phase offset is rate limited.
[6]
Phase build-out
A phase build-out transition was made to the currently active reference.
[5]
Freq lock
The DPLL has achieved frequency lock.
[4]
Phase lock
The DPLL has achieved phase lock.
[3]
Loop switching
The DPLL is in the process of a reference switchover.
[2]
Holdover
The DPLL is in holdover mode.
[1]
Active
The DPLL is active (that is, operating in a closed-loop condition)
[0]
Free running
The DPLL is free running (that is, operating in an open-loop condition)
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